17,425 research outputs found
Programmable rate modem utilizing digital signal processing techniques
The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulation. The preferred implementation technique is an all digital one which utilizes as much digital signal processing (DSP) as possible. Here design tradeoffs in each portion of the modulator and demodulator subsystem are outlined, and viable circuit approaches which are easily repeatable, have low implementation losses and have low production costs are identified. The research involved for this study was divided into nine technical papers, each addressing a significant region of concern in a variable rate modem design. Trivial portions and basic support logic designs surrounding the nine major modem blocks were omitted. In brief, the nine topic areas were: (1) Transmit Data Filtering; (2) Transmit Clock Generation; (3) Carrier Synthesizer; (4) Receive AGC; (5) Receive Data Filtering; (6) RF Oscillator Phase Noise; (7) Receive Carrier Selectivity; (8) Carrier Recovery; and (9) Timing Recovery
A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects
Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2
Implementation Aspects of a Transmitted-Reference UWB Receiver
In this paper, we discuss the design issues of an ultra wide band (UWB) receiver targeting a single-chip CMOS implementation for low data-rate applications like ad hoc wireless sensor networks. A non-coherent transmitted reference (TR) receiver is chosen because of its small complexity compared to other architectures. After a brief recapitulation of the UWB fundamentals and a short discussion on the major differences between coherent and non-coherent receivers, we discuss issues, challenges and possible design solutions. Several simulation results obtained by means of a behavioral model are presented, together with an analysis of the trade-off between performance and complexity in an integrated circuit implementation
Fast synchronization 3R burst-mode receivers for passive optical networks
This paper gives a tutorial overview on high speed burst-mode receiver (BM-RX) requirements, specific for time division multiplexing passive optical networks, and design issues of such BM-RXs as well as their advanced design techniques. It focuses on how to design BM-RXs with short burst overhead for fast synchronization. We present design principles and circuit architectures of various types of burst-mode transimpedance amplifiers, burst-mode limiting amplifiers and burst-mode clock and data recovery circuits. The recent development of 10 Gb/s BM-RXs is highlighted also including dual-rate operation for coexistence with deployed PONs and on-chip auto reset generation to eliminate external timing-critical control signals provided by a PON medium access control. Finally sub-system integration and state-of-the-art system performance for 10 Gb/s PONs are reviewed
Operational experience, improvements, and performance of the CDF Run II silicon vertex detector
The Collider Detector at Fermilab (CDF) pursues a broad physics program at
Fermilab's Tevatron collider. Between Run II commissioning in early 2001 and
the end of operations in September 2011, the Tevatron delivered 12 fb-1 of
integrated luminosity of p-pbar collisions at sqrt(s)=1.96 TeV. Many physics
analyses undertaken by CDF require heavy flavor tagging with large charged
particle tracking acceptance. To realize these goals, in 2001 CDF installed
eight layers of silicon microstrip detectors around its interaction region.
These detectors were designed for 2--5 years of operation, radiation doses up
to 2 Mrad (0.02 Gy), and were expected to be replaced in 2004. The sensors were
not replaced, and the Tevatron run was extended for several years beyond its
design, exposing the sensors and electronics to much higher radiation doses
than anticipated. In this paper we describe the operational challenges
encountered over the past 10 years of running the CDF silicon detectors, the
preventive measures undertaken, and the improvements made along the way to
ensure their optimal performance for collecting high quality physics data. In
addition, we describe the quantities and methods used to monitor radiation
damage in the sensors for optimal performance and summarize the detector
performance quantities important to CDF's physics program, including vertex
resolution, heavy flavor tagging, and silicon vertex trigger performance.Comment: Preprint accepted for publication in Nuclear Instruments and Methods
A (07/31/2013
A new coherent demodulation technique for land-mobile satellite communications
An advanced coherent demodulation technique is described for land mobile satellite (LMS) communications. The proposed technique features a combined narrow/wind band dual open loop carrier phase estimator, which is effectively able to compensate the fast carrier phase fluctuation by fading with sacrificing a phase slip rate. Also included is the realization of quick carrier and clock reacquisition after shadowing by taking open loop structure. Its bit error rate (BER) performance is superior to that of existing detection schemes, showing a BER of 1 x 10(exp -2) at 6.3 dB E sub b/N sub o over the Rician channel with 10 dB C/M and 200 Hz (1/16 modulation rate) fading pitch f sub d for QPSK. The proposed scheme consists of a fast response carrier recovery and a quick bit timing recovery with an interpolation. An experimental terminal model was developed to evaluate its performance at fading conditions. The results are quite satisfactory, giving prospects for future LMS applications
Shuttle/TDRSS modelling and link simulation study
A Shuttle/TDRSS S-band and Ku-band link simulation package called LinCsim was developed for the evaluation of link performance for specific Shuttle signal designs. The link models were described in detail and the transmitter distortion parameters or user constraints were carefully defined. The overall link degradation (excluding hardware degradations) relative to an ideal BPSK channel were given for various sets of user constraint values. The performance sensitivity to each individual user constraint was then illustrated. The effect of excessive Spacelab clock jitter on the return link BER performance was also investigated as was the problem of subcarrier recovery for the K-band Shuttle return link signal
RAPID CLOCK RECOVERY ALGORITHMS FOR DIGITAL MAGNETIC RECORDING AND DATA COMMUNICATIONS
SIGLEAvailable from British Library Document Supply Centre-DSC:DXN024293 / BLDSC - British Library Document Supply CentreGBUnited Kingdo
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