Modeling and Design of High-Performance DC-DC Converters

The goal of the research that was pursued during this PhD is to eventually facilitate the development of high-performance, fast-switching DC-DC converters. High-switching frequency in switching mode power supplies (SMPS) can be exploited by reducing the output voltage ripple for the same size of passives (mainly inductors and capacitors) and improve overall system performance by providing a voltage supply with less unwanted harmonics to the subsystems that they support. The opposite side of the trade-off is also attractive for designers as the same amount of ripple can be achieved with smaller values of inductance and/or capacitance which can result in a physically smaller and potentially cheaper end product. Another benefit is that the spectrum of the resulting switching noise is shifted to higher frequencies which in turn allows designers to push the corner frequency of the control loop of the system higher without the switching noise affecting the behavior of the system. This in turn, is translated to a system capable of responding faster to strong transients that are common in modern systems that may contain microprocessors or other electronics that tend to consume power in bursts and may even require the use of features like dynamic voltage scaling to minimize the overall consumption of the system. While the analysis of the open loop behavior of a DC-DC converter is relatively straightforward, it is of limited usefulness as they almost always operate in closed loop and therefore can suffer from degraded stability. Therefore, it is important to have a way to simulate their closed loop behavior in the most efficient manner possible. The first chapter is dedicated to a library of technology-agnostic high-level models that can be used to improve the efficiency of transient simulations without sacrificing the ability to model and localize the different losses. This work also focuses further in fixed-frequency converters that employ Peak Current Mode Control (PCM) schemes. PCM schemes are frequently used due to their simple implementation and their ability to respond quickly to line transients since any change of the battery voltage is reflected in the slope of the rising inductor current which in turn is monitored by a fast internal control loop that is closed with the help of a current sensor. Most existing models for current sensors assume that they behave in an ideal manner with infinite bandwidth and ideal constant gain. These assumptions tend to be in significant error as the minimum on-time of the sensor and therefore the settling time requirements of the sensor are reduced. Some sensing architectures, like the ones that approximate the inductor current with the high-side switch current, can be even more complex to analyze as they require the use of extended masking time to prevent spike currents caused by the switch commutation to be injected to the output of the sensor and therefore the signal processing blocks of the control loop. In order to solve this issue, this work also proposes a current sensor model that is compatible with time averaged models of DC-DC converters and is able to predict the effects of static and transient non-idealities of the block on the behavior of a PCM DC-DC converter. Lastly, this work proposes a new 40 V, 6 A, fully-integrated, high-side current sensing circuit with a response time of 51 . The proposed sensor is able to achieve this performance with the help of a feedback resistance emulation technique that prevents the sensor from debiasing during its masking phase which tends to extend the response time of similar fully integrated sensors

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Improving Phase Change Memory (PCM) and Spin-Torque-Transfer Magnetic-RAM (STT-MRAM) as Next-Generation Memories: A Circuit Perspective

In the memory hierarchy of computer systems, the traditional semiconductor memories Static RAM (SRAM) and Dynamic RAM (DRAM) have already served for several decades as cache and main memory. With technology scaling, they face increasingly intractable challenges like power, density, reliability and scalability. As a result, they become less appealing in the multi/many-core era with ever increasing size and memory-intensity of working sets. Recently, there is an increasing interest in using emerging non-volatile memory technologies in replacement of SRAM and DRAM, due to their advantages like non-volatility, high device density, near-zero cell leakage and resilience to soft errors. Among several new memory technologies, Phase Change Memory (PCM) and Spin-Torque-Transfer Magnetic-RAM (STT-MRAM) are most promising candidates in building main memory and cache, respectively. However, both of them possess unique limitations that preventing them from being effectively adopted. In this dissertation, I present my circuit design work on tackling the limitations of PCM and STT-MRAM. At bit level, both PCM and STT-MRAM suffer from excessive write energy, and PCM has very limited write endurance. For PCM, I implement Differential Write to remove large number of unnecessary bit-writes that do not alter the stored data. It is then extended to STT-MRAM as Early Write Termination, with specific optimizations to eliminate the overhead of pre-write read. At array level, PCM enjoys high density but could not provide competitive throughput due to its long write latency and limited number of read/write circuits. I propose a Pseudo-Multi-Port Bank design to exploit intra-bank parallelism by recycling and reusing shared peripheral circuits between accesses in a time-multiplexed manner. On the other hand, although STT-MRAM features satisfactory throughput, its conventional array architecture is constrained on density and scalability by the pitch of the per-column bitline pair. I propose a Common-Source-Line Array architecture which uses a shared source-line along the row, essentially leaving only one bitline per column. For these techniques, I provide circuit level analyses as well as architecture/system level and/or process/device level discussions. In addition, relevant background and work are thoroughly surveyed and potential future research topics are discussed, offering insights and prospects of these next-generation memories

Modelling of a Buck converter with adaptive modulation and design of related driver stage

This thesis concerns the modelling of a buck converter with peak current mode control, and adaptive PWM/PFM (constant Ton) and provides a small signal model, derived from steady-state averaging, for all the operative regions of the converter, and used for stability analysis and parametric optimization. Eventually the design of a driver stage is proposed, with segmentation, dead time control and zero cross detection as main functionalities to improve efficienc

In-memory computing with emerging memory devices: Status and outlook

Supporting data for "In-memory computing with emerging memory devices: status and outlook", submitted to APL Machine Learning

An Energy-efficient Capacitive-Memristive Content Addressable Memory

Content addressable memory is popular in the field of intelligent computing systems with its searching nature. Emerging CAMs show a promising increase in pixel density and a decrease in power consumption than pure CMOS solutions. This article introduced an energy-efficient 3T1R1C TCAM cooperating with capacitor dividers and RRAM devices. The RRAM as a storage element also acts as a switch to the capacitor divider while searching for content. CAM cells benefit from working parallel in an array structure. We implemented a 64 x 64 array and digital controllers to perform with an internal built-in clock frequency of 875MHz. Both data searches and reads take 3x clock cycles. Its worst average energy for data match is reported to be 1.71 fJ/bit-search and the worst average energy for data miss is found with 4.69 fJ/bit-search. The prototype is simulated and fabricated in 0.18 um technology with in-lab RRAM post-processing. Such memory explores the charge domain searching mechanism and can be applied to data centers that are power-hungry.Comment: This work has been submitted to the IEEE TCAS-I for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessibl

Development of an integrated opto-electric biosensor to dynamically examine cytometric proliferation and cytotoxicity

My doctoral research has focused on the development of microscale optical techniques for examining micro/bio fluidics. Preliminary work measured the velocity field in a microchannel, by optical slicing, using Confocal Laser Scanning Microscopy (CLSM). Next, Optical Serial Sectioning Microscopy (OSSM) was applied to examine thermometry by detecting the free Brownian motion of nano-particles suspended in mediums at different temperatures. An extension of this work used objective-based Total Internal Reflection Fluorescence Microscopy (TIRFM) to examine the hindered Brownian motion of nano-particles that were very close to a solid surface (within 1 mm). An optically transparent and electrically conductive Indium Tin Oxide (ITO) biosensor and an integrated dynamic live cell imaging system were developed to dynamically examine changes in cell coverage area, cell morphology, cell-substrate adhesion, and cell-cell interaction. To our knowledge this is the first sensor capable of conducting simultaneous optical and electrical measurements. This system consists of an incubator, which keeps cells viable by providing the necessary environmental conditions (37 °C temperature and 5 % CO2), and multiple microscopy techniques, including multispectrum Interference Reflection Microscopy (MS-IRM), TIRFM, Epi-fluorescence Microscopy, Phase Contrast Microscopy (PCM), and Differential Interference Contrast Microscopy (DICM). Along with investigations of cytometric proliferation including cellular barrier functions, in vitro cytotoxicity experiments were also conducted to examine the effect of a drug (cytochalasin D, a toxic agent) on cellular motility and cellular morphology. These cytotoxicity results give us a fundamental understanding of the cellular processes induced by the drug, which will be invaluable in the search for methods of preventing metastases. In this research, MS-IRM is used to examine the focal contacts and the gap morphology between cells and substrates, DICM is used to examine the coverage area of cells, and impedance measurements are used to correlate these two parameters. Advances in the understanding of vascular bio-transport in endothelial cells will have an impact on many aspects of cell biology, tissue engineering, and pharmacology. Particularly important will be the ability to test the popular hypothesis that the cell barrier function is regulated by specific cytoskeleton elements controlling intercellular and extracellular coupling