12,541 research outputs found
Dynamic Yield Analysis and Enhancement of FPGA Reconfigurable Memory Systems
This paper addresses the issues of field programmable gate arrays (FPGA) reconfigurable memory systems with faulty physical memory cells and proposes yield measurement techniques. Static yield (i.e., the yield which does not take into account the inherited redundancy utilization for repair) and dynamic yield (i.e., the yield which takes into account the inherited redundancy utilization for repair) of FPGA reconfigurable memory systems and their characteristics are extensively analyzed. Yield enhancement of conventional memory systems relies on additional redundancy, but FPGA reconfigurable memory systems have inherited redundancy and customizability. Thus, they can accommodate numerous target memory configurations, and redundant memory cells, if any, can be used as spares to enhance the dynamic yield of a target memory configuration. Three fundamental strategies are introduced and analyzed; i.e., redundant bit utilization, redundant word utilization, and a combination of both. Mathematical analysis of those techniques also has been conducted to study their effects on the yield. Selecting the most yield enhancing logical memory configuration which can accommodate a target memory requirement among the candidate configurations is referred to as optimal fitting. Optimal fitting algorithms for single configuration fitting, sequential reconfiguration system fitting, and concurrent reconfiguration system fitting are investigated based on the proposed yield analysis techniques
Dynamic Yield Analysis and Enhancement of FPGA Reconfigurable Memory Systems
This paper addresses the issues of field programmable gate arrays (FPGA) reconfigurable memory systems with faulty physical memory cells and proposes yield measurement techniques. Static yield (i.e., the yield which does not take into account the inherited redundancy utilization for repair) and dynamic yield (i.e., the yield which takes into account the inherited redundancy utilization for repair) of FPGA reconfigurable memory systems and their characteristics are extensively analyzed. Yield enhancement of conventional memory systems relies on additional redundancy, but FPGA reconfigurable memory systems have inherited redundancy and customizability. Thus, they can accommodate numerous target memory configurations, and redundant memory cells, if any, can be used as spares to enhance the dynamic yield of a target memory configuration. Three fundamental strategies are introduced and analyzed; i.e., redundant bit utilization, redundant word utilization, and a combination of both. Mathematical analysis of those techniques also has been conducted to study their effects on the yield. Selecting the most yield enhancing logical memory configuration which can accommodate a target memory requirement among the candidate configurations is referred to as optimal fitting. Optimal fitting algorithms for single configuration fitting, sequential reconfiguration system fitting, and concurrent reconfiguration system fitting are investigated based on the proposed yield analysis techniques
Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration
As microfluidics-based biochips become more complex, manufacturing yield will
have significant influence on production volume and product cost. We propose an
interstitial redundancy approach to enhance the yield of biochips that are
based on droplet-based microfluidics. In this design method, spare cells are
placed in the interstitial sites within the microfluidic array, and they
replace neighboring faulty cells via local reconfiguration. The proposed design
method is evaluated using a set of concurrent real-life bioassays.Comment: Submitted on behalf of EDAA (http://www.edaa.com/
Efficient algorithms for reconfiguration in VLSI/WSI arrays
The issue of developing efficient algorithms for reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources is discussed. The models discussed consist of a set of identical processors embedded in a flexible interconnection structure that is configured in the form of a rectangular grid. An array grid model based on single-track switches is considered. An efficient polynomial time algorithm is proposed for determining feasible reconfigurations for an array with a given distribution of faulty processors. In the process, it is shown that the set of conditions in the reconfigurability theorem is not necessary. A polynomial time algorithm is developed for finding feasible reconfigurations in an augmented single-track model and in array grid models with multiple-track switche
Digital implementation of the cellular sensor-computers
Two different kinds of cellular sensor-processor architectures are used nowadays in various
applications. The first is the traditional sensor-processor architecture, where the sensor and the
processor arrays are mapped into each other. The second is the foveal architecture, in which a
small active fovea is navigating in a large sensor array. This second architecture is introduced
and compared here. Both of these architectures can be implemented with analog and digital
processor arrays. The efficiency of the different implementation types, depending on the used
CMOS technology, is analyzed. It turned out, that the finer the technology is, the better to use
digital implementation rather than analog
Interconnect yield analysis and fault tolerance for field programmable gate arrays
Imperial Users onl
Evaluation of a Field Programmable Gate Array Circuit Reconfiguration System
This research implements a circuit reconfiguration system (CRS) to reconfigure a field programmable gate array (FPGA) in response to a faulty configurable logic block (CLB). It is assumed that the location of the fault is known and the CLB is moved according to one of four replacement methods: column left, column right, row up, and row down. Partial reconfiguration of the FPGA is done through the Joint Test Action Group (JTAG) port to produce the desired logic block movement. The time required to accomplish the reconfiguration is measured for each method in both clear and congested areas of the FPGA. The measured data indicate that there is no consistently better replacement method, regardless of the circuit congestion or location within the FPGA. Thus, given a specific location in the FPGA, there is no preferred replacement method that will result in the lowest reconfiguration time
Field Effect Transistor Nanosensor for Breast Cancer Diagnostics
Silicon nanochannel field effect transistor (FET) biosensors are one of the most promising technologies in the development of highly sensitive and label-free analyte detection for cancer diagnostics. With their exceptional electrical properties and small dimensions, silicon nanochannels are ideally suited for extraordinarily high sensitivity. In fact, the high surface-to-volume ratios of these systems make single molecule detection possible. Further, FET biosensors offer the benefits of high speed, low cost, and high yield manufacturing, without sacrificing the sensitivity typical for traditional optical methods in diagnostics. Top down manufacturing methods leverage advantages in Complementary Metal Oxide Semiconductor (CMOS) technologies, making richly multiplexed sensor arrays a reality. Here, we discuss the fabrication and use of silicon nanochannel FET devices as biosensors for breast cancer diagnosis and monitoring
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