Network-on-Chip Synchronization

Technology scaling has enabled the number of cores within a System on Chip (SoC) to increase significantly. Globally Asynchronous Locally Synchronous (GALS) systems using Dynamic Voltage and Frequency Scaling (DVFS) operate each of these cores on distinct and dynamic clock domains. The main communication method between these cores is increasingly more likely to be a Network-on-Chip (NoC). Typically, the interfaces between these clock domains experience multi-cycle synchronization latencies due to their use of “brute-force” synchronizers. This dissertation aims to improve the performance of NoCs and thereby SoCs as a whole by reducing this synchronization latency. First, a survey of NoC improvement techniques is presented. One such improvement technique: a multi-layer NoC, has been successfully simulated. Given how one of the most commonly used techniques is DVFS, a thorough analysis and simulation of brute-force synchronizer circuits in both current and future process technologies is presented. Unfortunately, a multi-cycle latency is unavoidable when using brute-force synchronizers, so predictive synchronizers which require only a single cycle of latency have been proposed. To demonstrate the impact of these predictive synchronizer circuits at a high level, multi-core system simulations incorporating these circuits have been completed. Multiple forms of GALS NoC configurations have been simulated, including multi-synchronous, NoC-synchronous, and single-synchronizer. Speedup on the SPLASH benchmark suite was measured to directly quantify the performance benefit of predictive synchronizers in a full system. Additionally, Mean Time Between Failures (MTBF) has been calculated for each NoC synchronizer configuration to determine the reliability benefit possible when using predictive synchronizers

Gradual Synchronization

A synchronization solution is developed in order to allow finer grained segmentation of clock domains on a chip. This solution incorporates computation into the synchronization overhead time and is called Gradual Synchronization. With Gradual Synchronization as a synchronization method the design space of a chip could easily mix both asynchronous and synchronous blocks of logic, paving the way for wider use of asynchronous logic design

Biological rhythms, chronodisruption and chrono-enhancement: The role of physical activity as synchronizer in correcting steroids circadian rhythm in metabolic dysfunctions and cancer

This is an Accepted Manuscript of an article published by Taylor & Francis in Chronobiology International on 28 June 2018, available online: http://www.tandfonline.com/10.1080/07420528.2018.1475395.Rhythms can be observed at all levels of the biologic integration in humans. The observation that a biological or physiological variable shows a circadian rhythm can be explained by several multifactorial systems including external (exogenous), internal (endogenous) and psychobiological (lifestyle) mechanisms. Our body clock can be synchronized with the environment by external factors, called “synchronizers”, i.e. the light–dark cycle, but it is also negatively influenced by some pathological conditions or factors, called “chronodisruptors,” i.e. aging or low physical activity (PA). The desynchronization of a 24-h rhythm in a chronic manner has been recently defined “chronodisruption” or “circadian disruption.” A very large number of hormonal variables, such as adrenal and gonadal stress steroids, are governed by circadian rhythmicity. Such hormones, in normal conditions, show a peak in the first part of the day, while their typical diurnal fluctuations are totally out of sync in subjects affected by cancer or metabolic diseases, such as obesity, diabetes and metabolic syndrome. In general, a flatter slope with altered peaks in cortisol and testosterone circadian rhythms has been observed in pathological individuals. PA, specifically chronic exercise, seems to play a key role as synchronizer for the whole circadian system in such pathologies even if specific data on steroids circadian pattern are still sparse and contradictory. Recently, it has been proposed that low-intensity chronic PA could be an effective intervention to decrease morning cortisol levels in pathological subjects. The standardization of all confounding factors is needed to reach more clear evidence-based results

Design of robust asynchronous reconfigurable controllers for parallel synchronization using embedded graphs

PhD Thesis: This is a revised version received 24/5/16. The definitive version is the print copy in the Research Reserve Collection of the University LibrarySynchronization is a key System-on-Chip (SoC) design issue in modern technologies. As the number of operating points under consideration increases, specifications which are capable of altering key parameters such as the time available for synchronization and Mean Time Between Failures (MTBF) in response to input from the user/system become desirable. This thesis explores how a combination of parallelism and scheduling, referred to as wagging, can be utilized to construct schedulers for synchronizer designs which are capable of pooling the gain-bandwidth products of their composite devices, in order to satisfy this requirement. In this work, we explore the ways in which the areas of graph theory and reconfigurable hardware design can be applied to generate both combinational and sequential scheduler designs, which satisfy the behavior requirement above. Further to this point, this work illustrates that such a scheduler is primarily comprised of an interrupt subsystem, and a reconfigurable token ring. This thesis explores how both of these components can be controlled in absence of a clock signal, as well as the design challenges inherent to each part. The final noteworthy issue in this study is with regard to the flow control of data in a parallel synchronizer that incorporates a First-In First-Out (FIFO) buffer to decouple the reading and writing operations from each other. Such a structure incurs penalties if the data rates on both sides are not well matched. This work presents a method by which combinations of serial and parallel reading operations are used to minimize this mismatch

Transdisciplinary unifying implications of circadian findings in the 1950s

A few puzzles relating to a small fraction of my endeavors in the 1950s are summarized herein, with answers to a few questions of the Editor-in-Chief, to suggest that the rules of variability in time complement the rules of genetics as a biological variability in space. I advocate to replace truisms such as a relative constancy or homeostasis, that have served bioscience very well for very long. They were never intended, however, to lower a curtain of ignorance over everyday physiology. In raising these curtains, we unveil a range of dynamics, resolvable in the data collection and as-one-goes analysis by computers built into smaller and smaller devices, for a continued self-surveillance of the normal and for an individualized detection of the abnormal. The current medical art based on spotchecks interpreted by reference to a time-unqualified normal range can become a science of time series with tests relating to the individual in inferential statistical terms. This is already doable for the case of blood pressure, but eventually should become possible for many other variables interpreted today only based on the quicksand of clinical trials on groups. These ignore individual differences and hence the individual's needs. Chronomics (mapping time structures) with the major aim of quantifying normalcy by dynamic reference values for detecting earliest risk elevation, also yields the dividend of allowing molecular biology to focus on the normal as well as on the grossly abnormal

Physically informed runtime verification for cyber physical systems

textCyber-physical systems (CPS) are an integration of computation with physical processes. CPS have gained popularity both in industry and the research community and are represented by many varied mission critical applications. Debugging CPS is important, but the intertwining of the cyber and physical worlds makes it very difficult. Formal methods, simulation, and testing are not sufficient in guarantee required correctness. Runtime Verification (RV) provides a perfect complement. However the state of the art in RV lacks either efficiency or expressiveness, and very few RV technologies are specifically designed for CPS. The CPS community requires an intuitive, expressive, and practical RV middleware toolset to improve the state of the art. In this proposal, I take an incremental and realistic approach to identify and address the research challenges in CPS verification and validation. Firstly, I carry out a systematic analysis of the state of the art and state of the practice in verifying and validating CPS using a structured on-line survey, semi-structured interviews, and an exhaustive literature review. From the findings obtained, I identify the key research gaps and propose research directions to address these research gaps. My second work is to work on the most pertinent research direction proposed, which is to provide a practical and physically informed runtime verification tool-sets specifically designed for CPS as a sound foundation to the trial and error practice identified as the state of the art in verifying and validating CPS. I create an expressive yet intuitive language (BraceAssertion) to specify CPS properties. I develop a framework (BraceBind) to supplement CPS runtime verification with a real time simulation environment which is able to integrate physical models from various simulation platform. Based on BraceAssertion and BraceBind, which collectively captures the combination of logical content and physical environment, I develop a practical runtime verification framework (Brace), which is efficient, effective, expressive in capturing both local and global properties, and guarantee predictable runtime monitors behavior even with unpredictable surge of events. I evaluate the tool-set with increasingly complex real CPS applications of smart agent systems.Electrical and Computer Engineerin

Study of efficient transmission and reception of image-type data using millimeter waves

Evaluation of signal processing and modulation techniques for transmission and reception of image type data via millimeter wave relay satellite

Doctor of Philosophy

dissertationPortable electronic devices will be limited to available energy of existing battery chemistries for the foreseeable future. However, system-on-chips (SoCs) used in these devices are under a demand to offer more functionality and increased battery life. A difficult problem in SoC design is providing energy-efficient communication between its components while maintaining the required performance. This dissertation introduces a novel energy-efficient network-on-chip (NoC) communication architecture. A NoC is used within complex SoCs due it its superior performance, energy usage, modularity, and scalability over traditional bus and point-to-point methods of connecting SoC components. This is the first academic research that combines asynchronous NoC circuits, a focus on energy-efficient design, and a software framework to customize a NoC for a particular SoC. Its key contribution is demonstrating that a simple, asynchronous NoC concept is a good match for low-power devices, and is a fruitful area for additional investigation. The proposed NoC is energy-efficient in several ways: simple switch and arbitration logic, low port radix, latch-based router buffering, a topology with the minimum number of 3-port routers, and the asynchronous advantages of zero dynamic power consumption while idle and the lack of a clock tree. The tool framework developed for this work uses novel methods to optimize the topology and router oorplan based on simulated annealing and force-directed movement. It studies link pipelining techniques that yield improved throughput in an energy-efficient manner. A simulator is automatically generated for each customized NoC, and its traffic generators use a self-similar message distribution, as opposed to Poisson, to better match application behavior. Compared to a conventional synchronous NoC, this design is superior by achieving comparable message latency with half the energy

Digital desing for neuroporphic bio-inspired vision processing.

Artificial Intelligence (AI) is an exciting technology that flourished in this century. One of the goals for this technology is to give learning ability to computers. Currently, machine intelligence surpasses human intelligence in specific domains. Besides some conventional machine learning algorithms, Artificial Neural Networks (ANNs) is arguably the most exciting technology that is used to bring this intelligence to the computer world. Due to ANN’s advanced performance, increasing number of applications that need kind of intelligence are using ANN. Neuromorphic engineers are trying to introduce bio-inspired hardware for efficient implementation of neural networks. This hardware should be able to simulate a vast number of neurons in real-time with complex synaptic connectivity while consuming little power. The work that has been done in this thesis is hardware oriented, so it is necessary for the reader to have a good understanding of the hardware that is used for developments in this thesis. In this chapter, we provide a brief overview of the hardware platforms that are used in this thesis. Afterward, we explain briefly the contributions of this thesis to the bio-inspired processing research line

DeepDeMod: BPSK Demodulation Using Deep Learning Over Software-Defined Radio

In wireless communication, signal demodulation under non-ideal conditions is one of the important research topic. In this paper, a novel non-coherent binary phase shift keying demodulator based on deep neural network, namely DeepDeMod, is proposed. The proposed scheme makes use of neural network to decode the symbols from the received sampled signal. The proposed scheme is developed to demodulate signal under fading channel with additive white Gaussian noise along with hardware imperfections, such as phase and frequency offset. The time varying nature of hardware imperfections and channel poses a additional challenge in signal demodulation. In order to address this issue, additionally we propose transfer learning based DeepDeMod scheme. Pilot symbols along with data is transmitted in a packet which is used to learn the time varying parameters from the pilot reception followed by data demodulation. Results show that compared with the conventional demodulators and other machine learning based demodulators, our proposed DeepDeMod provides significantly better performance in term of bit error rate. We also implement the proposed DeepDeMod on software defined radio and present the experimental results