The Direct Summation of Totally Self-Checking Checkers

A new technique for reducing the complexity of designing Totally Self-Checking (TSC) checkers for m-out-of-n codes is presented. The method is based on the partitioning of the input variables into r classes, then partitioning the code groups generated into Z output partitions. Comparison with earlier results reveals improvements in design simplicity and logic and testing complexity. This thesis also presents a new method of TSC checker design where a j-level m1/n1 code and a k-level m2/n2 code TSC checker are directly summed to form a max [j,k]-level (m1 + m2) / (n1 + n2) TSC checker. A library of m/n code TSC checkers can then be used as building blocks for other m/n code TSC checkers

Design of CMOS PSCD circuits and checkers for stuck-at and stuck-on faults

[[abstract]]We present in this paper an approach to designing partially strongly code-disjoint (PSCD) CMOS circuits and checkers, considering transistor stuck-on faults in addition to gate-level stuck-at faults. Our design-for-testability (DFT) technique requires only a small number of extra transistors for monitoring abnormal static currents, coupled with a simple clocking scheme, to detect the stuck-on faults concurrently. The DFT circuitry not only can detect the faults in the functional circuit but also can detect or tolerate faults in itself, making it a good candidate for checker design. Switch and circuit level simulations were performed on a sample circuit, and a sample 4-out-of-8 code checker chip using the proposed technique has been designed, fabricated, and tested, showing the correctness of the method. Performance penalty is reduced by a novel BiCMOS checker circuit.[[fileno]]2030108010057[[department]]電機工程學

Efficient design of CMOS TSC checkers

This paper considers the design of an efficient, robustly testable, CMOS Totally Self-Checking (TSC) Checker for k-out-of-2k codes. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers under the stuck-open fault model due to timing skews and arbitrary delays in the circuit. A new four level design using CMOS primitive gates (NAND, NOR, INVERTERS) is presented. This design retains its properties under the stuck-open fault model. Additionally, this method offers an impressive reduction (greater than 70 percent) in gate count, gate inputs, and test set size when compared to the existing method. This implementation is easily realizable and is based on Anderson's technique. A thorough comparative study has been made on the proposed implementation and Kundu's implementation and the results indicate that the proposed one is better than Kundu's in all respects for k-out-of-2k codes

LSI/VLSI design for testability analysis and general approach

The incorporation of testability characteristics into large scale digital design is not only necessary for, but also pertinent to effective device testing and enhancement of device reliability. There are at least three major DFT techniques, namely, the self checking, the LSSD, and the partitioning techniques, each of which can be incorporated into a logic design to achieve a specific set of testability and reliability requirements. Detailed analysis of the design theory, implementation, fault coverage, hardware requirements, application limitations, etc., of each of these techniques are also presented

Techniques for efficiently implementing totally self-checking checkers in MOS technology

This paper presents some new techniques for reducing the transistor count oof MOS implementations of totally self-checking (TSC) checkers. The techniques are (1) transfer of fanouts, (2) removal of inverters and (3) use of multi-level realizations of functions. These techniques also increase the speed of the circuit and may reduce the number of required tests. Their effectiveness has been demonstrated by applying them to m-out-of-n and Berger code checkers. Impressive reductions of up to 90% in the transistor count in some cases have been obtained for the MOS implementation of these checkers. This directly translates into saving of chip area.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/26970/1/0000537.pd

Синтез самопроверяемых схем встроенного контроля на основе метода логического дополнения до равновесного кода «2 из 4»

The article explores the peculiarities of self-checking integrated control circuits synthesis by the Boolean complement method based on the "2-out-of-4'' constant-weight code. The article describes the features of integrated control circuits implementation by the Boolean complement method. It is noted that it is possible to synthesize the structures of discrete devices, which have less structural redundancy than in situation of the control circuit implementation by the method of duplication. The effect in structural redundancy reducing is achieved by minimizing the complexity of the control logic block technical implementation and using checkers that are simpler in their structures than the comparator in the system of duplication. The article proposes a method of the integrated control circuit organization based on determining the values of control functions taking into account the maintenance of testability of elements of addition by modulo two in the Boolean complement block and the checker of the "2-out-of-4" code.Исследуются особенности синтеза самопроверяемых схем встроенного контроля по методу логического дополнения на основе равновесного кода «2 из 4». Описываются особенности реализации схем встроенного контроля по методу логического дополнения. Отмечается возможность синтеза структур дискретных устройств, имеющих меньшую структурную избыточность, чем при реализации схемы контроля по методу дублирования. Эффект в снижении структурной избыточности достигается за счет минимизации сложности технической реализации блока контрольной логики и использования более простых по своим структурам тестеров, чем компаратор в системе дублирования. Предлагается способ организации схемы встроенного контроля, основанный на доопределении значений контрольных функций с учетом обеспечения тестируемости элементов сложения по модулю два в блоке логического дополнения и тестера кода «2 из 4»

Reliability Driven Synthesis of Sequential Circuits

Coordinated Science Laboratory was formerly known as Control Systems LaboratorySemiconductor Research Corporation / SRC 95-DP-109Joint Services Electronics Program / N00014-90-J-127