IC design for reliability

textAs the feature size of integrated circuits goes down to the nanometer scale, transient and permanent reliability issues are becoming a significant concern for circuit designers. Traditionally, the reliability issues were mostly handled at the device level as a device engineering problem. However, the increasing severity of reliability challenges and higher error rates due to transient upsets favor higher-level design for reliability (DFR). In this work, we develop several methods for DFR at the circuit level. A major source of transient errors is the single event upset (SEU). SEUs are caused by high-energy particles present in the cosmic rays or emitted by radioactive contaminants in the chip packaging materials. When these particles hit a N+/P+ depletion region of an MOS transistor, they may generate a temporary logic fault. Depending on where the MOS transistor is located and what state the circuit is at, an SEU may result in a circuit-level error. We analyze SEUs both in combinational logic and memories (SRAM). For combinational logic circuit, we propose FASER, a Fast Analysis tool of Soft ERror susceptibility for cell-based designs. The efficiency of FASER is achieved through its static and vector-less nature. In order to evaluate the impact of SEU on SRAM, a theory for estimating dynamic noise margins is developed analytically. The results allow predicting the transient error susceptibility of an SRAM cell using a closedform expression. Among the many permanent failure mechanisms that include time-dependent oxide breakdown (TDDB), electro-migration (EM), hot carrier effect (HCE), and negative bias temperature instability (NBTI), NBTI has recently become important. Therefore, the main focus of our work is NBTI. NBTI occurs when the gate of PMOS is negatively biased. The voltage stress across the gate generates interface traps, which degrade the threshold voltage of PMOS. The degraded PMOS may eventually fail to meet timing requirement and cause functional errors. NBTI becomes severe at elevated temperatures. In this dissertation, we propose a NBTI degradation model that takes into account the temperature variation on the chip and gives the accurate estimation of the degraded threshold voltage. In order to account for the degradation of devices, traditional design methods add guard-bands to ensure that the circuit will function properly during its lifetime. However, the worst-case based guard-bands lead to significant penalty in performance. In this dissertation, we propose an effective macromodel-based reliability tracking and management framework, based on a hybrid network of on-chip sensors, consisting of temperature sensors and ring oscillators. The model is concerned specifically with NBTIinduced transistor aging. The key feature of our work, in contrast to the traditional tracking techniques that rely solely on direct measurement of the increase of threshold voltage or circuit delay, is an explicit macromodel which maps operating temperature to circuit degradation (the increase of circuit delay). The macromodel allows for costeffective tracking of reliability using temperature sensors and is also essential for enabling the control loop of the reliability management system. The developed methods improve the over-conservatism of the device-level, worstcase reliability estimation techniques. As the severity of reliability challenges continue to grow with technology scaling, it will become more important for circuit designers/CAD tools to be equipped with the developed methods.Electrical and Computer Engineerin

Non-invasive power gating techniques for bursty computation workloads using micro-electro-mechanical relays

PhD ThesisElectrostatically-actuated Micro-Electro-Mechanical/Nano-Electro- Mechanical (MEM/NEM) relays are promising devices overcoming the energy-efficiency limitations of CMOS transistors. Many exploratory research projects are currently under way investigating the mechanical, electrical and logical characteristics of MEM/NEM relays. One particular issue that this work addresses is the need for a scalable and accurate physical model of the MEM/NEM switches that can be plugged into the standard EDA software. The existing models are accurate and detailed but they suffer from the convergence problem. This problem requires finding ad-hoc workarounds and significantly impacts the designer’s productivity. In this thesis we propose a new simplified Verilog-AMS model. To test scalability of the proposed model we cross-checked it against our analysis of a range of benchmark circuits. Results show that, compared to standard models, the proposed model is sufficiently accurate with an average of 6% error and can handle larger designs without divergence. This thesis also investigates the modelling, designing and optimization of various MEM/NEM switches using 3D Finite Element Analysis (FEA) performed by the COMSOL multiphysics simulation tool. An extensive parametric sweep simulation is performed to study the energy-latency trade-offs of MEM/NEM relays. To accurately simulate MEMS/NEMS-based digital circuits, a Verilog-AMS model is proposed based on the evaluated parameters obtained from the multiphysics simulation tool. This allows an accurate calibration of the MEM/NEM relays with a significant reduction in simulation speed compared to that of 3D FEA exercised on COMSOL tool. The effectiveness of two power gating approaches in asynchronous micropipelines is also investigated using MEM/NEM switches and sleep transistors in reducing idle power dissipation with a particular target throughput. Sleep transistors are traditionally used to power gate idle circuits, however, these transistors have fundamental limitations in their effectiveness. Alternatively, MEM/NEM relays with zero leakage current can achieve greater energy savings under a certain data rate and design architecture. An asynchronous FIR filter 4 phase bundled data handshake protocol is presented. Implementation is accomplished in 90nm technology node and simulation exercised at various data rates and design complexities. It was demonstrated that our proposed approach offers 69% energy improvements at a data rate 1KHz compared to 39% of the previous work. The current trends for greater heterogeneity in future Systems-on- Chip (SoC) do not only concern their functionality but also their timing and power aspects. The increasing diversity of timing and power supply conditions, and associated concurrently operating modes, within an SoC calls for more efficient power delivery networks (PDN) for battery operated devices. This is especially important for systems with mixed duty cycling, where some parts are required to work regularly with low-throughput while other parts are activated spontaneously, i.e. in bursts. To improve their reaction time vs energy efficiency, this work proposes to incorporate a power-switching network based on MEM relays to switch the SoC power-performance state (PPS) into an active mode while eliminating the leakage current when it is idle. Results show that even with today0s large and high pull-in voltages, a MEM-relay-based power switching network (PSN) can achieve a 1000x savings in energy compared to its CMOS counterpart for low duty cycle. A simple case of optimising an on-chip charge pump required to switch-on the relay has been investigated and its energy-latency overhead has been evaluated. Heterogeneous many-core systems are increasingly being employed in modern embedded platforms for high throughput at low energy cost considerations. These applications typically exhibit bursty workloads that provide opportunities to minimize system energy. CMOS-based power gating circuitry, typically consisting of sleep transistors, is used as an effective technique for idle energy reduction in such applications. However, these transistors contribute high leakage current when driving large capacitive loads, making effective energy minimization challenging. This thesis proposes a novel MEMS-based idle energy control approach. Core to this approach is an integrated sleep mode management based on the performance-energy states and bursty workloads indicated by the performance counters. A number of PARSEC benchmark applications are used as case studies of bursty workloads, including CPU- and memory- intensive ones. These applications are exercised on an Exynos 5422 heterogeneous many-core platform, engineered with a performance counter facilities, showing 55.5% energy savings compared with an on-demand governor. Furthermore, an extensive trade-off analysis demonstrates the comparative advantages of the MEMS-based controller, including zero-leakage current and non-invasive implementations suitable for commercial off-the-shelf systems.Higher committee of education development in Iraq (HCED

On Energy Efficient Computing Platforms

In accordance with the Moore's law, the increasing number of on-chip integrated transistors has enabled modern computing platforms with not only higher processing power but also more affordable prices. As a result, these platforms, including portable devices, work stations and data centres, are becoming an inevitable part of the human society. However, with the demand for portability and raising cost of power, energy efficiency has emerged to be a major concern for modern computing platforms. As the complexity of on-chip systems increases, Network-on-Chip (NoC) has been proved as an efficient communication architecture which can further improve system performances and scalability while reducing the design cost. Therefore, in this thesis, we study and propose energy optimization approaches based on NoC architecture, with special focuses on the following aspects. As the architectural trend of future computing platforms, 3D systems have many bene ts including higher integration density, smaller footprint, heterogeneous integration, etc. Moreover, 3D technology can signi cantly improve the network communication and effectively avoid long wirings, and therefore, provide higher system performance and energy efficiency. With the dynamic nature of on-chip communication in large scale NoC based systems, run-time system optimization is of crucial importance in order to achieve higher system reliability and essentially energy efficiency. In this thesis, we propose an agent based system design approach where agents are on-chip components which monitor and control system parameters such as supply voltage, operating frequency, etc. With this approach, we have analysed the implementation alternatives for dynamic voltage and frequency scaling and power gating techniques at different granularity, which reduce both dynamic and leakage energy consumption. Topologies, being one of the key factors for NoCs, are also explored for energy saving purpose. A Honeycomb NoC architecture is proposed in this thesis with turn-model based deadlock-free routing algorithms. Our analysis and simulation based evaluation show that Honeycomb NoCs outperform their Mesh based counterparts in terms of network cost, system performance as well as energy efficiency.Siirretty Doriast

Ferroelectric Field Effect Transistor for Memory and Switch Applications

Silicon technology has advanced at exponential rates both in performances and productivity through the past four decades. However the limit of CMOS technology seems to be closer and closer and in the future we might see an increasing number of hybrid approaches where other technologies add to the CMOS performance, while maintaining a back-bone of CMOS logic. Ferro-electricity in ultra-thin films has been investigated as a credible candidate for nonvolatile memory thanks to the bistability of polarization. 1 transistor (1T) ferroelectric memory cells have been proposed and experimentally studied in order to reduce the size of 1T-1C (1Transistor-1Capacitor) design with consequent advantages in terms of size, read-out operation and costs. More recently ferroelectrics have been proposed by Salahuddin and Datta as dielectric materials in order to lower the 60mV/dec limit of the subthreshold swing (SS) in silicon Metal Oxide Semiconductor Field Effect Transistors, MOSFETs. The objective of this thesis is to study the ferroelectric transistor performance for both memory and switch application. For this purpose different Ferroelectric Field Effect Transistors, Fe-FETs, structures have been designed, fabricated and characterized. An organic ferroelectric polymer, vinylidene fluoride trifluorethylene, P(VDF-TrFE), of 100nm and 40nm thickness has been successfully integrated into the gate stack of bulk and SOI MOSFET and, later, on a Tunnel FET, TFET, structure. The 1T ferroelectric FET memory cells have shown a programming time in the order of ms at 9V as programming voltage. The retention of a few seconds, however, is the main limiting factor for the usage of this device for NV-memory applications. The retention failure mechanisms have been studied and investigated for future improvement. For the first time this work experimentally demonstrates that a subthreshold swing lower than 60mv/dec can be achieved in a ferroelectric transistor thanks to the voltage amplification arising from the ferroelectric material. This unique finding has been first measured in a 40nm P(VDF-TrFE)/10nm SiO2 gate stack MOSFET and then, confirmed, in a 100nm P(VDF-TrFE)/10nm SiO2 gate MOSFET with an intermediate contact between the two dielectrics. This internal node contact allows the study of the voltage amplification due to the ferroelectric material. Finally a temperature study of the performance of a ferroelectric Fully Depleted Silicon on Insulator, FD SOI, transistor has been done. A model based on Landau's theory has been carried out and it has been experimentally validated for both the subthreshold and the strong inversion regions. It has been demonstrated for the first time that, because of the divergence of the ferroelectric permittivity at the Curie temperature, Tc, a ferroelectric transistor has a maximum and a minimum, respectively of its transconductance and subthreshold swing, at Tc

Stochastic Models of Surface Limited Electronic and Heat Transport in Metal and Semiconductor Contacts, Wires, and Sheets — Micro to Nano

We introduce novel statistical simulation approaches to include the e ect of surface roughness in coupled mechanical, electronic and thermal processes in N/MEMS and semiconductor devices in the 10 nm - 1 m range. A model is presented to estimate roughness rms and autocorrelation L from experimental surfaces and edges, and subsequently generate statistical series of rough geometrical devices from these observable parameters. Using such series of rough electrodes under Holm's theory, we present a novel simulation framework which predicts a contact resistance of 80 m in MEMS gold-gold micro-contacts, for applied pressures above 0.3 mN on 1 m 1 m surfaces. The non-contacting state of such devices is simulated through statistical Monte Carlo iterations on percolative networks to derive a time to electro-thermal failure through electrical discharges in the gas insulating metal electrodes. The observable parameters L and are further integrated in semi-classical solutions to the electronic and thermal Boltzman transport equation (BTE), and we show roughness limited heat and electronic transport in rough semiconductor nanowires and nano-ribbons. In this scope, we model for the rst time electrostatically con ned nanowires, where a reduction of electron - surface scattering leads to enhanced mobility in comparison to geometrical nanowires. In addition, we show extremely low thermal conductivity in Si, GaAs, and Ge nanowires down to 0.1 W/m/K for thin Ge wires with 56 nm width and = 3 nm. The dependency of thermal conductivity in (D= )2 leads to possible application in the eld of thermoelectric devices. For rough channels of width below 10 nm, electronic transport is additionally modeled using a novel non-parabolic 3D recursive Green function scheme, leading to an estimation of reduced electronic transmission in rough semiconductor wires based on the quantum nature of charge carriers. Electronic and thermal simulation schemes are nally extended to such 2D semiconductor materials as graphene, where low thermal conductivity is approximated below 1000 W/m/K for rough suspended graphene ribbons in accordance with recent experiments