Distributed clock generator for synchronous SoC using ADPLL network

International audienceThis paper presents a novel architecture of on-chip clock generation employing a network of oscillators synchronized by the distributed all-digital PLLs (ADPLLs). The implemented prototype has 16 clocking domains operating synchronously in a frequency range of 1.1-2.4 GHz. The synchronization error between the neighboring clock domains is less than 60 ps. The fully digital architecture of the generation offers flexibility and efficient synchronization control suitable for use in synchronous SoCs

Digital controlled oscillator (DCO) for all digital phase-locked loop (ADPLL) – a review

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL

Designing a Ring Oscillator Using Nanotechnology through Cadence Virtuoso

This paper presents the design and simulation of a ring oscillator using nanotechnology and the Cadence Virtuoso platform. As feature sizes continue to shrink, new design methodologies are required to account for quantum effects that become prominent at the nanoscale. This paper utilizes predictive technology models for a 45nm process to design a three-stage ring oscillator with minimum channel lengths. The ring oscillator design is optimized through careful selection of transistor characteristics and layout considerations. Post-layout simulations demonstrate functionality with oscillation frequency and phase noise matching expected theoretical values. The completed design provides a demonstration of a basic analog circuit block implemented with nanoscale technology. &nbsp

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Ultra-Wideband CMOS Transceiver Front-End for Bio-Medical Radar Sensing

Since the Federal Communication Commission released the unlicensed 3.1-10.6 GHz frequency band for commercial use in early 2002, the ultra wideband (UWB) has developed from an emerging technology into a mainstream research area. The UWB technology, which utilizes wide spectrum, opens a new era of possibility for practical applications in radar sensing, one of which is the human vital sign monitoring. The aim of this thesis is to study and research the possibility of a new generation humanrespiration monitoring sensor using UWB radar technology and to develop a new prototype of UWB radar sensor for system-on-chip solutions in CMOS technology. In this thesis, a lowpower Gaussian impulse UWB mono-static radar transceiver architecture is presented. The UWB Gaussian pulse transmitter and receiver are implemented and fabricated using 90nm CMOS technology. Since the energy of low order Gaussian pulse is mostly condensed at lower frequency, in order to transmit the pulse in a very efficient way, higher order Gaussian derivative pulses are desired as the baseband signal. This motivates the advancement of the design into UWB high-order pulse transmitter. Both the Gaussian impulse UWB transmitter and Gaussian higher-order impulse UWB transmitter take the low-power and high-speed advantage of digital circuit to generate different waveforms. The measurement results are analyzed and discussed. This thesis also presents a low-power UWB mono-static radar transceiver architecture exploiting the full benefit of UWB bandwidth in radar sensing applications. The transceiver includes a full UWB band transmitter, an UWB receiver front-end, and an on-chip diplexer. The non-coherent UWB transmitter generates pulse modulated baseband signals at different carrier frequencies within the designated 3-10 GHz band using a digitally controlled pulse generator. The test shows the proposed radar transceiver can detect the human respiration pattern within 50 cm distance. The applications of this UWB radar sensing solution in commercialized standard CMOS technology include constant breathing pattern monitoring for gated radiation therapy, realtime monitoring of patients, and any other breathing monitoring. The research paves the way to wireless technology integration with health care and bio-sensor network

Asymmetric 5.5 GHz Three-Stage Voltage-Controlled Ring-Oscillator in 65 nm CMOS Technology

The current trend of increasing the complexity of hardware accelerators to improve their functionality is highlighting the problem of sharing a high-frequency clock signal for all integrated modules. As the clock itself is becoming the main limitation to the performance of accelerators, in this manuscript, we present the design of an asymmetric Ring Oscillator-Voltage-Controlled Oscillator (RO-VCO) based on the Current Mode Logic architecture. The RO-VCO was designed on commercial-grade 65 nm CMOS technology, and it is capable of driving large capacitance loads, avoiding the need for additional buffers for clock-trees, reducing the silicon area and power consumption. The proposed RO-VCO is composed of three closed-loop differential and asymmetrical stages, and it is able to tune the working frequency in the range from 4.72 GHz to 6.12 GHz. The phase noise and a figure of merit of −103.2 dBc/Hz and −186 dBc/Hz were obtained at 1 MHz offset from the 5.5 GHz carrier. In this article, the analytical model, full custom schematic, and layout of the proposed RO-VCO are presented and discussed in detail together with the experimental electrical and thermal characterization of the fabricated device

A Bang-Bang All-Digital PLL for Frequency Synthesis

abstract: Phase locked loops are an integral part of any electronic system that requires a clock signal and find use in a broad range of applications such as clock and data recovery circuits for high speed serial I/O and frequency synthesizers for RF transceivers and ADCs. Traditionally, PLLs have been primarily analog in nature and since the development of the charge pump PLL, they have almost exclusively been analog. Recently, however, much research has been focused on ADPLLs because of their scalability, flexibility and higher noise immunity. This research investigates some of the latest all-digital PLL architectures and discusses the qualities and tradeoffs of each. A highly flexible and scalable all-digital PLL based frequency synthesizer is implemented in 180 nm CMOS process. This implementation makes use of a binary phase detector, also commonly called a bang-bang phase detector, which has potential of use in high-speed, sub-micron processes due to the simplicity of the phase detector which can be implemented with a simple D flip flop. Due to the nonlinearity introduced by the phase detector, there are certain performance limitations. This architecture incorporates a separate frequency control loop which can alleviate some of these limitations, such as lock range and acquisition time.Dissertation/ThesisM.S. Electrical Engineering 201

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2