A verified equivalent-circuit model for slotwaveguide modulators

We formulate and experimentally validate an equivalent-circuit model based on distributed elements to describe the electric and electro-optic (EO) properties of travellingwave silicon-organic hybrid (SOH) slot-waveguide modulators. The model allows to reliably predict the small-signal EO frequency response of the modulators exploiting purely electrical measurements of the frequency-dependent RF transmission characteristics. We experimentally verify the validity of our model, and we formulate design guidelines for an optimum trade-off between optical loss due to free-carrier absorption (FCA), electro-optic bandwidth, and {\pi}-voltage of SOH slot-waveguide modulators

Characterization and Design of Millimeter-Wave Complementary Metal-Oxide-Semiconductor Components, and Broadband Low-Noise Amplifiers

This thesis focuses on the characterization and design of millimeter-wave CMOS components and broadband low-noise amplifiers. In the design of millimeter-wave circuits, accurate characterization of on-wafer active and passive components is of great importance. In this thesis, several well-known de-embedding techniques, which are used to characterize on-wafer devices, are reviewed, and their accuracies are investigated. A new de-embedding method for extracting the high frequency characteristics of a device-under-test is presented and applied to test structures manufactured in 28-nm CMOS technology. Excellent agreement is achieved between the simulated and experimental data up to 110 GHz, indicating that the proposed technique is an effective tool in characterization of mm-wave on-wafer components. Furthermore, design of active and passive components, which are used in the millimeter-wave low-noise amplifier circuit, is presented. Layout optimization techniques to improve the high frequency performances of these components are explained in detail. Simulation results are presented to demonstrate the performances of individual components. Finally, several issues concerning millimeter-wave low-noise amplifier design are discussed, such as stability, noise figure and different amplifier topologies. A three-stage full W-band low-noise amplifier achieving a flat gain of 15 dB and 5.5 dB noise figure over a very wideband is designed. Extensive simulation results showing the performance of the amplifier are presented

Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications

Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung List of symbols and abbreviations Acknowledgement 1. Introduction 2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias 3. Fabrication of BiCMOS & Silicon Interposer with TSVs 4. Characterization of BiCMOS Embedded Through-Silicon Vias 5. Applications 6. Conclusion and Future Work 7. Appendix 8. Publications & Patents 9. Bibliography 10. List of Figures and Table

Comparison of De-embedding Methods for Long Millimeter and Sub-Millimeter-Wave Integrated Circuits

National audienceThis paper compares several de-embedding methods over millimeter and sub-millimeter wave frequen-cies in integrated technology. These methods are compared for S-CPW transmission lines considered as device under test. From these comparisons we propose an effective way to de-embed transmission lines. A method called "Half-Thru de-embedding method" is especially discussed. The SCPW transmission line model and results are obtained from Ansys HFSS Simulations in BiCMOS 55-nm integrat-ed technology

On-Wafer Microwave De-Embedding Techniques

Wireless communication technology has kept evolving into higher frequency regime to take advantage of wider data bandwidth and higher speed performance. Successful RF circuit design requires accurate characterization of on-chip devices. This greatly relies on robust de-embedding technique to completely remove surrounding parasitics of pad and interconnects that connect device to measurement probes. Complex interaction of fixture parasitic at high frequency has imposed extreme challenges to de-embedding particularly for lossy complementary metal oxide semiconductor (CMOS) device. A generalized network de-embedding technique that avoids any inaccurate lumped and transmission line assumptions on the pad and interconnects of the test structure is presented. The de-embedding strategy has been validated by producing negligible de-embedding error (<−50 dB) on the insertion loss of the zero-length THRU device. It demonstrates better accuracy than existing de-embedding techniques that are based on lumped pad assumption. For transistor characterization, the de-embedding reference plane could be further shifted to the metal fingers with additional Finger OPEN-SHORT structures. The resulted de-embedded RF parameters of CMOS transistor show good scalability across geometries and negligible frequency dependency of less than 3% for up to 100 GHz. The results reveal the importance of accounting for the parasitic effect of metal fingers for transistor characterization

Méthodes de mesure pour l’analyse vectorielle aux fréquences millimétriques en technologie intégrée

This thesis focuses on the study of vectorial measurement methods for analysing microelectronic circuits in integrated technology at millimeter wave frequencies. Current calibration and de-embedding methods are less precise for successfully extracting the intrinsic parameters of devices and circuits at millimeter wave frequencies, while the targeted operating frequencies are above 100 GHz. This is especially true for the characterization of passive devices such as propagation lines. The initial motivation of this thesis work was to explain the exact origin of the additional loss measured in Slow-Wave Coplanar Waveguides (S-CPW) lines at millimeter wave frequencies. Was it a problem of raw measurement or a problem of de-embedding method, which underestimates the losses? Or was it a problem of insufficient modeling of the effects of adjacent cells, or even the creation of a perturbation mode of propagation?This work consists of estimating many de-embedding methods beyond 65 GHz and classifies these methods into three groups to be able to compare them in a meaningful way. This study was conducted in three phases.In the first phase, we compared all the de-embedding methods with known electrical model parasitics of pad/accessline. This phase identifies the optimal conditions to use and apply these de-embedding methods.In the second phase, the modeling of test structures is performed using a 3D electromagnetic simulator based on finite element method. This phase tested the robustness of the methods and considered an original de-embedding method called Half-Thru de-embedding method. This method gives comparable results to the TRL method, which remains the most effective method. However, it remains difficult to explain the origin of additional losses obtained in measured S-CPW line.A third modeling phase was analysed to take into account the measurement of probes and the adjacent cells near our device under test. More than 80 test structures were designed in AMS 0.35 μm CMOS technology to compare the different de-embedding methods and analyse the link with adjacent cells, measuring probes and perturbation mode of propagation.Finally, this work has identified a number of precautions to consider for the attention of microelectronic circuit designers wishing to characterize their circuit with precision beyond 110 GHz. It also helped to establish Half-Thru Method de-embedding method, which is not based on electrical model, unlike other methods.Cette thèse porte sur l’étude des méthodes de mesure pour l’analyse vectorielle des circuits microélectroniques en technologie intégrée aux fréquences millimétriques. Pour réussir à extraire les paramètres intrinsèques de circuits réalisés aux longueurs d'ondes millimétriques, les méthodes actuelles de calibrage et de de-embedding sont d'autant moins précises que les fréquences de fonctionnement visées augmentent au-delà de 100 GHz notamment. Cela est d’autant plus vrai pour la caractérisation des dispositifs passifs tels que des lignes de propagation. La motivation initiale de ces travaux de thèse venait du fait qu'il était difficile d'expliquer l’origine exacte des pertes mesurées pour des lignes coplanaires à ondes lentes (lignes S-CPW) aux fréquences millimétriques. Etait-ce un problème de mesure brute, un problème de méthode de-embedding qui sous-estime les pertes, une modélisation insuffisante des effets des cellules adjacentes, ou encore la création d'un mode de propagation perturbatif ?Le travail a principalement consisté à évaluer une dizaine de méthodes de de-embedding au-delà de 65 GHz et à classifier ces méthodes en 3 groupes pour pouvoir les comparer de manière pertinente. Cette étude s’est déroulée en 3 phases.Dans la première phase, il s’agissait de comparer les méthodes de de-embedding tout en maitrisant les modèles électriques des plots et des lignes d’accès. Cette phase a permis de dégager les conditions optimales d’utilisation pour pouvoir appliquer ces différentes méthodes de de-embedding.Dans la deuxième phase, la modélisation des structures de test a été réalisée à l’aide d’un simulateur électromagnétique 3D basé sur la méthode des éléments finis. Cette phase a permis de tester la robustesse des méthodes et d’envisager une méthode de-embedding originale nommée Half-Thru Method. Cette méthode donne des résultats comparables à la méthode TRL, méthode qui reste la plus performante actuellement. Cependant il reste difficile d'expliquer l'origine des pertes supplémentaires obtenues notamment dans la mesure des lignes à ondes lentes S-CPW.Une troisième phase de modélisation a alors consisté à prendre en compte les pointes de mesure et les cellules adjacentes à notre dispositif sous test. Plus de 80 structures de test ont été conçues en technologie AMS 0,35μm afin de comparer les différentes méthodes de de-embedding et d’en analyser les couplages avec les structures adjacentes, les pointes de mesure et les modes de propagation perturbatifs.Finalement, ce travail a permis de dégager un certain nombre de précautions à considérer à l’attention des concepteurs de circuits microélectroniques désirant caractériser leur circuit avec précision au-delà de 110 GHz. Il a également permis de mettre en place la méthode de de-embedding Half-Thru Method qui n'est basée sur aucun modèle électrique, au contraire des autres méthodes

Extension of 0.18µm standard CMOS technology operating range to the microwave and millimetre-wave regime

There is an increasing interest in building millimetre-wave circuits on standard digital complementary metal oxide semiconductor (CMOS) technology for applications such as wireless local area networks (WLAN), automotive radar and remote sensing. This stems from the existing low cost, well-developed, high yield infrastructure for mass production. The overall aim of this thesis is to extend the operating range of 0.18um standard logic CMOS technology to millimetre-wave regime. To this end, microwave and millimetre-wave design, optimisation and modelling methodologies for active and passive devices and low noise circuit implementation are described. As part of the evaluation, new systematic and modular ways of making high performance passive and active devices such as spiral inductors, slow-wave coplanar waveguide (CPW) transmission lines, comb capacitors and NMOS transistors are proposed, designed, simulated, fabricated, modelled and analysed. Small-signal and noise de-embedding techniques are developed and verified up to 110 GHz, providing an increased accuracy in the device model, leading to a robust design at millimetre-wave frequencies. Reduced substrate losses resulting in increased quality factor are presented for optimised spiral inductor designs, featuring patterned floating shield (PFS), enabling improved matching network and a reduced chip area. Based on the proposed shielded slow-wave CPW, both the line attenuation and structure length are decreased, resulting in a more compact and simplified circuit design. An optimised transistor design, aimed at reducing the layout parasitic effects, was realised. The optimisation led to a significant improvement in the gain and noise performance of the transistor, extending its operation beyond the cut-off frequency (ft). By combining all the optimised components, low noise amplifiers (LNAs) operating at 25 GHz and 40 GHz were implemented and compared. These LNAs demonstrate state-of-the-art performance, with the 40 GHz LNA exhibiting the highest gain and lowest noise performance of any LNA reported using 0.18um CMOS technology. On the other hand, the 25 GHz LNA showed a comparable performance to other reported results in literature using several topologies implemented in CMOS technology. These findings will provide a framework for expansion to smaller CMOS technology nodes with the view of extending to sub millimetre-wave frequencies

CMOS MESFET Cascode Amplifiers for RFIC Applications

abstract: There is an ever-increasing demand for higher bandwidth and data rate ensuing from exploding number of radio frequency integrated systems and devices. As stated in the Shannon-Hartley theorem, the maximum achievable data rate of a communication channel is linearly proportional to the system bandwidth. This is the main driving force behind pushing wireless systems towards millimeter-wave frequency range, where larger bandwidth is available at a higher carrier frequency. Observing the Moor’s law, highly scaled complementary metal–oxide–semiconductor (CMOS) technologies provide fast transistors with a high unity power gain frequency which enables operating at millimeter-wave frequency range. CMOS is the compelling choice for digital and signal processing modules which concurrently offers high computation speed, low power consumption, and mass integration at a high manufacturing yield. One of the main shortcomings of the sub-micron CMOS technologies is the low breakdown voltage of the transistors that limits the dynamic range of the radio frequency (RF) power blocks, especially with the power amplifiers. Low voltage swing restricts the achievable output power which translates into low signal to noise ratio and degraded linearity. Extensive research has been done on proposing new design and IC fabrication techniques with the goal of generating higher output power in CMOS technology. The prominent drawbacks of these solutions are an increased die area, higher cost per design, and lower overall efficiency due to lossy passive components. In this dissertation, CMOS compatible metal–semiconductor field-effect transistor (MESFETs) are utilized to put forward a new solution to enhance the power amplifier’s breakdown voltage, gain and maximum output power. Requiring no change to the conventional CMOS process flow, this low cost approach allows direct incorporation of high voltage power MESFETs into silicon. High voltage MESFETs were employed in a cascode structure to push the amplifier’s cutoff frequency and unity power gain frequency to the 5G and K-band frequency range. This dissertation begins with CMOS compatible MESFET modeling and fabrication steps, and culminates in the discussion of amplifier design and optimization methodology, parasitic de-embedding steps, simulation and measurement results, and high resistivity RF substrate characterization.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201