Floating-Gate Design and Linearization for Reconfigurable Analog Signal Processing

Analog and mixed-signal integrated circuits have found a place in modern electronics design as a viable alternative to digital pre-processing. With metrics that boast high accuracy and low power consumption, analog pre-processing has opened the door to low-power state-monitoring systems when it is utilized in place of a power-hungry digital signal-processing stage. However, the complicated design process required by analog and mixed-signal systems has been a barrier to broader applications. The implementation of floating-gate transistors has begun to pave the way for a more reasonable approach to analog design. Floating-gate technology has widespread use in the digital domain. Analog and mixed-signal use of floating-gate transistors has only become a rising field of study in recent years. Analog floating gates allow for low-power implementation of mixed-signal systems, such as the field-programmable analog array, while simultaneously opening the door to complex signal-processing techniques. The field-programmable analog array, which leverages floating-gate technologies, is demonstrated as a reliable replacement to signal-processing tasks previously only solved by custom design. Living in an analog world demands the constant use and refinement of analog signal processing for the purpose of interfacing with digital systems. This work offers a comprehensive look at utilizing floating-gate transistors as the core element for analog signal-processing tasks. This work demonstrates the floating gate\u27s merit in large reconfigurable array-driven systems and in smaller-scale implementations, such as linearization techniques for oscillators and analog-to-digital converters. A study on analog floating-gate reliability is complemented with a temperature compensation scheme for implementing these systems in ever-changing, realistic environments

Integrated reference circuits for low-power capacitive sensor interfaces

This thesis consists of nine publications and an overview of the research topic, which also summarizes the work. The research described in this thesis concentrates on the design of low-power sensor interfaces for capacitive 3-axis micro-accelerometers. The primary goal throughout the thesis is to optimize power dissipation. Because the author made the main contribution to the design of the reference and power management circuits required, the overview part is dominated by the following research topics: current, voltage, and temperature references, frequency references, and voltage regulators. After an introduction to capacitive micro-accelerometers, the work describes the typical integrated readout electronics of a capacitive sensor on the functional level. The readout electronics can be divided into four different functional parts, namely the sensor readout itself, signal post-processing, references, and power management. Before the focus is shifted to the references and further to power management, different ways to realize the sensor readout are briefly discussed. Both current and voltage references are required in most analog and mixed-signal systems. A bandgap voltage reference, which inherently uses at least one current reference, is practical for the generation of an accurate reference voltage. Very similar circuit techniques can be exploited when implementing a temperature reference, the need for which in the sensor readout may be justified by the temperature compensation, for example. The work introduces non-linear frequency references, namely ring and relaxation oscillators, which are very suitable for the generation of the relatively low-frequency clock signals typically needed in the sensor interfaces. Such oscillators suffer from poor jitter and phase noise performance, the quantities of which also deserve discussion in this thesis. Finally, the regulation of the supply voltage using linear regulators is considered. In addition to extending the battery life by providing a low quiescent current, the regulator must be able to supply very low load currents and operate without off-chip capacitors

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

AMiBA Wideband Analog Correlator

A wideband analog correlator has been constructed for the Yuan-Tseh Lee Array for Microwave Background Anisotropy. Lag correlators using analog multipliers provide large bandwidth and moderate frequency resolution. Broadband IF distribution, backend signal processing and control are described. Operating conditions for optimum sensitivity and linearity are discussed. From observations, a large effective bandwidth of around 10 GHz has been shown to provide sufficient sensitivity for detecting cosmic microwave background variations.Comment: 28 pages, 23 figures, ApJ in press

Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters

In this dissertation, time-based signal processing techniques and their applications in oversampling and noise-shaping data converters are examined. These techniques demonstrate the ability to shift the burden of high performance analog circuits from the compressed voltage-domain to the augmented time-domain. First, the potential of high order noise-shaping and phase-domain feedback in time-to-digital converters (TDCs) is explored. A prototype phase reference, second-order continuous-time delta-sigma TDC for sensor applications was fabricated in 90nm CMOS and achieves 64 dB dynamic range in 1MHz signal bandwidth. Second, an ultra-high performance oscillator-based delta-sigma modulator architecture is investigated. The proposed circuit is a third-order continuous-time PLL-Based Delta-Sigma Modulator with simulated 77 dB SNDR in 40MHz signal bandwidth with OSR of 16, and is fabricated in 65nm CMOS

Low-voltage low-power continuous-time delta-sigma modulator designs

Ph.DDOCTOR OF PHILOSOPH

A Low-Power Silicon-Photomultiplier Readout ASIC for the CALICE Analog Hadronic Calorimeter

The future e + e − collider experiments, such as the international linear collider, provide precise measurements of the heavy bosons and serve as excellent tests of the underlying fundamental physics. To reconstruct these bosons with an unprecedented resolution from their multi-jet final states, a detector system employing the particle flow approach has been proposed, requesting calorimeters with imaging capabilities. The analog hadron calorimeter based on the SiPM-on-tile technology is one of the highly granular candidates of the imaging calorimeters. To achieve the compactness, the silicon-photomultiplier (SiPM) readout electronics require a low-power monolithic solution. This thesis presents the design of such an application-specific integrated circuit (ASIC) for the charge and timing readout of the SiPMs. The ASIC provides precise charge measurement over a large dynamic range with auto-triggering and local zero-suppression functionalities. The charge and timing information are digitized using channel-wise analog-to-digital and time-to-digital converters, providing a fully integrated solution for the SiPM readout. Dedicated to the analog hadron calorimeter, the power-pulsing technique is applied to the full chip to meet the stringent power consumption requirement. This work also initializes the commissioning of the calorimeter layer with the use of the designed ASIC. An automatic calibration procedure has been developed to optimized the configuration settings for the chip. The new calorimeter base unit with the designed ASIC has been produced and its functionality has been tested