Anticipated verbal feedback induces altruistic behavior

A distinctive feature of humans compared to other species is the high rate of cooperation with non-kin. One explanation is that humans are motivated by concerns for social esteem. In this paper we experimentally investigate the impact of anticipated verbal feedback on altruistic behavior. We study pairwise interactions in which one subject, the “divider”, decides how to split a sum of money between herself and a recipient. Thereafter, the recipient can send an unrestricted anonymous message to the divider. The subjects’ relationship is anonymous and one-shot to rule out any reputation effects. Compared to a control treatment without feedback messages, donations increase substantially when recipients can communicate. With verbal feedback, the fraction of zero donations decreases from about 40% to about 20%, and there is a corresponding increase in the fraction of equal splits from about 30% to about 50%. Recipients who receive no money almost always express disapproval of the divider, sometimes strongly and in foul language. Following an equal split, almost all recipients praise the divider. The results suggest that anticipated verbal rewards and punishments play a role in promoting altruistic behavior among humans.Punishment; Approval; Disapproval; Dictator game; Altruism; Communication; Verbal feedback

Pipelining Of Double Precision Floating Point Division And Square Root Operations On Field-programmable Gate Arrays

Many space applications, such as vision-based systems, synthetic aperture radar, and radar altimetry rely increasingly on high data rate DSP algorithms. These algorithms use double precision floating point arithmetic operations. While most DSP applications can be executed on DSP processors, the DSP numerical requirements of these new space applications surpass by far the numerical capabilities of many current DSP processors. Since the tradition in DSP processing has been to use fixed point number representation, only recently have DSP processors begun to incorporate floating point arithmetic units, even though most of these units handle only single precision floating point addition/subtraction, multiplication, and occasionally division. While DSP processors are slowly evolving to meet the numerical requirements of newer space applications, FPGA densities have rapidly increased to parallel and surpass even the gate densities of many DSP processors and commodity CPUs. This makes them attractive platforms to implement compute-intensive DSP computations. Even in the presence of this clear advantage on the side of FPGAs, few attempts have been made to examine how wide precision floating point arithmetic, particularly division and square root operations, can perform on FPGAs to support these compute-intensive DSP applications. In this context, this thesis presents the sequential and pipelined designs of IEEE-754 compliant double floating point division and square root operations based on low radix digit recurrence algorithms. FPGA implementations of these algorithms have the advantage of being easily testable. In particular, the pipelined designs are synthesized based on careful partial and full unrolling of the iterations in the digit recurrence algorithms. In the overall, the implementations of the sequential and pipelined designs are common-denominator implementations which do not use any performance-enhancing embedded components such as multipliers and block memory. As these implementations exploit exclusively the fine-grain reconfigurable resources of Virtex FPGAs, they are easily portable to other FPGAs with similar reconfigurable fabrics without any major modifications. The pipelined designs of these two operations are evaluated in terms of area, throughput, and dynamic power consumption as a function of pipeline depth. Pipelining experiments reveal that the area overhead tends to remain constant regardless of the degree of pipelining to which the design is submitted, while the throughput increases with pipeline depth. In addition, these experiments reveal that pipelining reduces power considerably in shallow pipelines. Pipelining further these designs does not necessarily lead to significant power reduction. By partitioning these designs into deeper pipelines, these designs can reach throughputs close to the 100 MFLOPS mark by consuming a modest 1% to 8% of the reconfigurable fabric within a Virtex-II XC2VX000 (e.g., XC2V1000 or XC2V6000) FPGA

Phase Locking Authentication for Scan Architecture

Scan design is a widely used Design for Testability (DfT) approach for digital circuits. It provides a high level of controllability and observability resulting in a high fault coverage. To achieve a high level of testability, scan architecture must provide access to the internal nodes of the circuit-under-test (CUT). This access however leads to vulnerability in the security of the CUT. If an unrestricted access is provided through a scan architecture, unlimited test vectors can be applied to the CUT and its responses can be captured. Such an unrestricted access to the CUT can potentially undermine the security of the critical information stored in the CUT. There is a need to secure scan architecture to prevent hardware attacks however a secure solution may limit the CUT testability. There is a trade-off between security and testability, therefore, a secure scan architecture without hindering its controllability and observability is required. Three solutions to secure scan architecture have been proposed in this thesis. In the first method, the tester is authenticated and the number of authentication attempts has been limited. In the second method, a Phase Locked Loop (PLL) is utilized to secure scan architecture. In the third method, the scan architecture is secured through a clock and data recovery (CDR) technique. This is a manuscript based thesis and the results of this study have been published in two conference proceedings. The latest results have also been prepared as an article for submission to a high rank conference

Design of ALU and Cache Memory for an 8 bit ALU

The design of an ALU and a Cache memory for use in a high performance processor was examined in this thesis. Advanced architectures employing increased parallelism were analyzed to minimize the number of execution cycles needed for 8 bit integer arithmetic operations. In addition to the arithmetic unit, an optimized SRAM memory cell was designed to be used as cache memory and as fast Look Up Table. The ALU consists of stand alone units for bit parallel computation of basic integer arithmetic operations. Addition and subtraction were performed using Kogge Stone parallel prefix hardware operating at 330MHz. A high performance multiplier was built using Radix 4 Modified Booth Encoder (MBE) and a Wallace Tree summation array. The multiplier requires single clock cycle for 8 bit integer multiplication and operates at a maximum frequency of 100MHz. Multiplicative division hardware was built for executing both integer division and square root. The division hardware computes 8-bit division and square root in 4 clock cycles. Multiplier forms the basic building block of all these functional units, making high level of resource sharing feasible with this architecture. The optimal operating frequency for the arithmetic unit is 70MHz. A 6T CMOS SRAM cell measuring 90 µm2 was designed using minimum size transistors. The layout allows for horizontal overlap resulting in effective area of 76 µm2 for an 8x8 array. By substituting equivalent bit line capacitance of P4 L1 Cache, the memory was simulated to have a read time of 3.27ns. An optimized set of test vectors were identified to enable high fault coverage without the need for any additional test circuitry. Sixteen test cases were identified that would toggle all the nodes and provide all possible inputs to the sub units of the multiplier. A correlation based semi automatic method was investigated to facilitate test case identification for large multipliers. This method of testability eliminates performance and area overhead associated with conventional testability hardware. Bottom up design methodology was employed for the design. The performance and area metrics are presented along with estimated power consumption. A set of Monte Carlo analysis was carried out to ensure the dependability of the design under process variations as well as fluctuations in operating conditions. The arithmetic unit was found to require a total die area of 2mm2 (approx.) in 0.35 micron process

High functionality reversible arithmetic logic unit

Energy loss is a big challenge in digital logic design primarily due to impending end of Moore’s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are limited. The main aim of this paper is to propose a new design of reversible ALU and enhance number of operations in it. This paper critically analyzes proposed ALU with existing designs and demonstrates increase in functionality with 56% reduction in gates, 17 % reduction in garbage lines, 92 % reduction in ancillary lines and 53 % reduction in quantum cost. The proposed ALU design is coded in Verilog HDL, synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2. RCViewer+ tool has been used to validate quantum cost of proposed design

Public key cryptosystems : theory, application and implementation

The determination of an individual's right to privacy is mainly a nontechnical matter, but the pragmatics of providing it is the central concern of the cryptographer. This thesis has sought answers to some of the outstanding issues in cryptography. In particular, some of the theoretical, application and implementation problems associated with a Public Key Cryptosystem (PKC).The Trapdoor Knapsack (TK) PKC is capable of fast throughput, but suffers from serious disadvantages. In chapter two a more general approach to the TK-PKC is described, showing how the public key size can be significantly reduced. To overcome the security limitations a new trapdoor was described in chapter three. It is based on transformations between the radix and residue number systems.Chapter four considers how cryptography can best be applied to multi-addressed packets of information. We show how security or communication network structure can be used to advantage, then proposing a new broadcast cryptosystem, which is more generally applicable.Copyright is traditionally used to protect the publisher from the pirate. Chapter five shows how to protect information when in easily copyable digital format.Chapter six describes the potential and pitfalls of VLSI, followed in chapter seven by a model for comparing the cost and performance of VLSI architectures. Chapter eight deals with novel architectures for all the basic arithmetic operations. These architectures provide a basic vocabulary of low complexity VLSI arithmetic structures for a wide range of applications.The design of a VLSI device, the Advanced Cipher Processor (ACP), to implement the RSA algorithm is described in chapter nine. It's heart is the modular exponential unit, which is a synthesis of the architectures in chapter eight. The ACP is capable of a throughput of 50 000 bits per second

Quantum Reality: Some Implications for Christian Theology

Problem Science (and also the myths concerning science) plays a dom inant role in contem porary society. In this study, the epistemological implications of quantum physics were investigated in order to clear aw ay some of the m yths concerning science. Method Q uantum mechanics was studied. After analyzing the basic postulates of quantum mechanics, several interpretations of the theory were examined. From quantum mechanics and its interpretations several epistemological implications were drawn. Results Several m yths concerning science were identified. These include perm anence of science, reductionism, determinism, absoluteness of logic, subject-object dichotomy, and the reality of the objects of a scientific model. Conclusions It is im portant for theologians to be aware of the m yths concerning science. The main benefit of quantum mechanics for theologians is in clearing away these myths firom the metaphysical conceptual space of theology

Animal Spirits: Affective and Deliberative Processes in Economic Behavior

The economic conception of human behavior assumes that a person has a single set of well-defined goals, and that the person's behavior is chosen to best achieve those goals. We develop a model in which a person's behavior is the outcome of an interaction between two systems: a deliberative system that assesses options with a broad, goal-based perspective, and an affective system that encompasses emotions and motivational drives. Our model provides a framework for understanding many departures from full rationality discussed in the behavioral-economics literature, and captures the familiar feeling of being "of two minds." And by focusing on factors that moderate the relative influence of the two systems, our model also generates a variety of novel testable predictions.

Design for Testability in a SerDes System

Testing an IC after fabrication helps ensure chip functionality. The techniques that consider the creation and utilization of tests inside the design flow are called Design for Testability. The present work evaluates and improves the test modules implementing BIST techniques created by César Limones 2016 thesis. It is important to mention that this work reports the first effort to make the full SerDes analog and digital module integration at ITESO. It required all the designers to work together in order to complete the SerDes chip design flow. In particular, the comparison data module design structure was redefined after the data flow was analyzed. The test modules simulation demonstrated the correct functionality while the timing reports with a 156.25MHz clock frequency, showed that the design is timing compliant. The SerDes final layout, which also integrated the test modules, was created with the analog modules placement and routing. However, there were issues with the routing over the analog modules, which produced an overlap on the internal metal layers. For this reason, it is encouraged to further research about the association and outcomes between the layout of the analog modules, the LEF file generation, and the analog module routing in the design flowRealizar pruebas en un chip luego de ser fabricado asegura la funcionalidad del circuito integrado. Las técnicas que contemplan la creación y aplicación de pruebas dentro del flujo de diseño del chip se llaman design for testability (diseño testable). Esta tesina evalúa y mejora los módulos de prueba que implementan técnicas de BIST, los cuales fueron creados por César Limones en la tesina del 2016. Es importante mencionar que este trabajo reporta los primeros esfuerzos realizados en el ITESO en integrar los módulos análogos y digitales que componen el SerDes. Se requirió del trabajo conjunto de todos los diseñadores para completar el flujo de diseño del chip del SerDes. En particular, la estructura del módulo de comparación fue totalmente modificada luego de que el flujo de datos fue analizado. Mediante la simulación de los módulos pruebas se demostró su correcto funcionamiento y los reportes de análisis de tiempo aplicados con un reloj a una frecuencia de 156.25MHz, mostraron que el diseño cumple con las restricciones de tiempo. El layout (diseño) final del SerDes, que integra también los módulos de pruebas, fue creado con la colocación y enrutamiento de los módulos análogos. Sin embargo, se presentaron problemas con el enrutamiento creado sobre el módulo análogo lo cual provocó un solapamiento con las capas de metal internas. Por esta razón, se exhorta a investigar sobre la asociación y resultados entre el layout de los módulos análogos, la generación del archivo LEF y el enrutamiento de los módulos análogos en el flujo de diseño.ITESO, A. C.Consejo Nacional de Ciencia y Tecnologí

Testability Properties of Divergent Trees

The testability of a class of regular circuits calleddivergent trees is investigated under a functional fault model. Divergent trees include such practical circuits as decoders anddemultiplexers. We prove that uncontrolled divergent trees aretestable with a fixed number of test patterns (C-testable) if andonly if the module function is surjective. Testable controlled treesare also surjective but require sensitizing vectors for errorpropagation. We derive the conditions for testing controlleddivergent trees with a test set whose size is proportional to thenumber of levels p found in the tree (L-testability). By viewing a tree as overlapping arrays of various types, we also deriveconditions for a controlled divergent tree to be C-testable. Typicaldecoders/demultiplexers are shown to only partially satisfy L- andC-testability conditions but a design modification that ensuresL-testability is demonstrated.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/43009/1/10836_2004_Article_146935.pd