13 research outputs found
๋์ญํญ ์ฆ๋ ๊ธฐ์ ์ ์ด์ฉํ ์ ๋ ฅ ํจ์จ์ ๊ณ ์ ์ก์ ์์คํ ์ค๊ณ
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2022.2. ์ ๋๊ท .The high-speed interconnect at the datacenter is being more crucial as 400 Gb Ethernet standards are developed. At the high data rate, channel loss re-quires bandwidth extension techniques for transmitters, even for short-reach channels. On the other hand, as the importance of east-to-west connection is rising, the data center architectures are switching to spine-leaf from traditional ones. In this trend, the number of short-reach optical interconnect is expected to be dominant. The vertical-cavity surface-emitting laser (VCSEL) is a com-monly used optical modulator for short-reach interconnect. However, since VCSEL has low bandwidth and nonlinearity, the optical transmitter also needs bandwidth-increasing techniques. Additionally, the power consumption of data centers reaches a point of concern to affect climate change. Therefore, this the-sis focuses on high-speed, power-efficient transmitters for data center applica-tions. Before the presenting circuit design, bandwidth extension techniques such as fractionally-spaced feed-forward equalizer (FFE), on-chip transmission line, inductive peaking, and T-coil are mathematically analyzed for their effec-tiveness.
For the first chip, a power and area-efficient pulse-amplitude modulation 4 (PAM-4) transmitter using 3-tap FFE based on a slow-wave transmission line is presented. A passive delay line is adopted for generating an equalizer tap to overcome the high clocking power consumption. The transmission line achieves a high slow-wave factor of 15 with double floating metal shields around the differential coplanar waveguide. The transmitter includes 4:1 multi-plexers (MUXs) and a quadrature clock generator for high-speed data genera-tion in a quarter-rate system. The 4:1 MUX utilizes a 2-UI pulse generator, and the input configuration is determined by qualitative analysis. The chip is fabri-cated in 65 nm CMOS technology and occupies an area of 0.151 mm2. The proposed transmitter system exhibits an energy efficiency of 3.03 pJ/b at the data rate of 48 Gb/s with PAM-4 signaling.
The second chip presents a power-efficient PAM-4 VCSEL transmitter using 3-tap FFE and negative-k T-coil. The phase interpolators (PIs) generate frac-tionally-spaced FFE tap and correct quadrature phase error. The PAM-4 com-bining 8:1 MUX is proposed rather than combining at output driver with double 4:1 MUXs to reduce serializing power consumption. T-coils at the internal and output node increase the bandwidth and remove inter-symbol interference (ISI). The negative-k T-coil at the output network increases the bandwidth 1.61 times than without T-coil. The VCSEL driver is placed on the high VSS domain for anode driving and power reduction. The chip is fabricated in 40 nm CMOS technology. The proposed VCSEL transmitter operates up to 48 Gb/s NRZ and 64 Gb/s PAM-4 with the power efficiency of 3.03 pJ/b and 2.09 pJ/b, respec-tively.400Gb ์ด๋๋ท ํ์ค์ด ๊ฐ๋ฐ๋จ์ ๋ฐ๋ผ ๋ฐ์ดํฐ ์ผํฐ์ ๊ณ ์ ์ํธ ์ฐ๊ฒฐ์ด ๋์ฑ ์ค์ํด์ง๊ณ ์๋ค. ๋์ ๋ฐ์ดํฐ ์๋์์์ ์ฑ๋ ์์ค์ ์ํด ๋จ๊ฑฐ๋ฆฌ ์ฑ๋์ ๊ฒฝ์ฐ์๋ ์ก์ ๊ธฐ์ ๋ํ ๋์ญํญ ํ์ฅ ๊ธฐ์ ์ด ํ์ํ๋ค. ํํธ, ๋ฐ์ดํฐ ์ผํฐ ๋ด ๋-์ ์ฐ๊ฒฐ์ ์ค์์ฑ์ด ๋์์ง๋ฉด์ ๋ฐ์ดํฐ ์ผํฐ ์ํคํ
์ฒ๊ฐ ๊ธฐ์กด์ ์ํคํ
์ฒ์์ ์คํ์ธ-๋ฆฌํ๋ก ์ ํ๋๊ณ ์๋ค. ์ด๋ฌํ ์ถ์ธ์์ ๋จ๊ฑฐ๋ฆฌ ๊ดํ ์ธํฐ์ปค๋ฅํธ์ ์๊ฐ ์ ์ฐจ ์ฐ์ธํด์ง ๊ฒ์ผ๋ก ์์๋๋ค. ์์ง ์บ๋นํฐ ํ๋ฉด ๋ฐฉ์ถ ๋ ์ด์ (VCSEL)๋ ์ผ๋ฐ์ ์ผ๋ก ๋จ๊ฑฐ๋ฆฌ ์ํธ ์ฐ๊ฒฐ์ ์ํด ์ฌ์ฉ๋๋ ๊ดํ ๋ชจ๋๋ ์ดํฐ์ด๋ค. VCSEL์ ๋ฎ์ ๋์ญํญ๊ณผ ๋น์ ํ์ฑ์ ๊ฐ์ง๊ณ ์๊ธฐ ๋๋ฌธ์, ๊ด ์ก์ ๊ธฐ๋ ๋์ญํญ ์ฆ๊ฐ ๊ธฐ์ ์ ํ์๋ก ํ๋ค. ๋ํ, ๋ฐ์ดํฐ ์ผํฐ์ ์ ๋ ฅ ์๋น๋ ๊ธฐํ ๋ณํ์ ์ํฅ์ ๋ฏธ์น ์ ์๋ ์ฐ๋ ค ์ง์ ์ ๋๋ฌํ๋ค. ๋ฐ๋ผ์, ๋ณธ ๋
ผ๋ฌธ์ ๋ฐ์ดํฐ ์ผํฐ ์์ฉ์ ์ํ ๊ณ ์ ์ ๋ ฅ ํจ์จ์ ์ธ ์ก์ ๊ธฐ์ ์ด์ ์ ๋ง์ถ๊ณ ์๋ค. ํ๋ก ์ค๊ณ๋ฅผ ์ ์ํ๊ธฐ ์ ์, ๋ถ๋ถ ๊ฐ๊ฒฉ ํผ๋-ํฌ์๋ ์ดํ๋ผ์ด์ (FFE), ์จ์นฉ ์ ์ก์ ๋ก, ์ธ๋ํฐ, T-์ฝ์ผ๊ณผ ๊ฐ์ ๋์ญํญ ํ์ฅ ๊ธฐ์ ์ ์ํ์ ์ผ๋ก ๋ถ์ํ๋ค.
์ฒซ ๋ฒ์งธ ์นฉ์ ์ ์ํ ์ ์ก์ ๋ก๋ฅผ ๊ธฐ๋ฐ์ผ๋ก ํ 3-ํญ FFE๋ฅผ ์ฌ์ฉํ๋ ์ ๋ ฅ ๋ฐ ๋ฉด์ ํจ์จ์ ์ธ ํ์ค-์งํญ-๋ณ์กฐ 4(PAM-4) ์ก์ ๊ธฐ๋ฅผ ์ ์ํ๋ค. ๋์ ํด๋ญ ์ ๋ ฅ ์๋น๋ฅผ ๊ทน๋ณตํ๊ธฐ ์ํด ์ดํ๋ผ์ด์ ํญ ์์ฑ์ ์ํด ์๋์์ ์ง์ฐ ๋ผ์ธ์ ์ฑํํ๋ค. ์ ์ก ๋ผ์ธ์ ์ฐจ๋ ๋์ผํ๋ฉด๋ํ๊ด ์ฃผ์์ ์ด์ค ํ๋กํ
๊ธ์ ์ฐจํ๋ฅผ ์ฌ์ฉํ์ฌ 15์ ๋์ ์ ๋ฌ์๋ ๊ฐ์ ๋ฅผ ๋ฌ์ฑํ๋ค. ์ก์ ๊ธฐ์๋ 4:1 ๋ฉํฐํ๋ ์(MUX)์ 4-์์ ํด๋ญ ์์ฑ๊ธฐ๊ฐ ํฌํจ๋์ด ์๋ค. 4:1 MUX๋ 2-UI ํ์ค ๋ฐ์๊ธฐ๋ฅผ ์ฌ์ฉํ๋ฉฐ, ์ ์ฑ ๋ถ์์ ์ํด ์
๋ ฅ ๊ตฌ์ฑ์ด ๊ฒฐ์ ๋๋ค. ์ด ์นฉ์ 65 nm CMOS ๊ธฐ์ ๋ก ์ ์๋์์ผ๋ฉฐ 0.151 mm2์ ๋ฉด์ ์ ์ฐจ์งํ๋ค. ์ ์๋ ์ก์ ๊ธฐ ์์คํ
์ PAM-4 ์ ํธ์ ํจ๊ป 48 Gb/s์ ๋ฐ์ดํฐ ์๋์์ 3.03 pJ/b์ ์๋์ง ํจ์จ์ ๋ณด์ฌ์ค๋ค.
๋ ๋ฒ์งธ ์นฉ์์๋ 3-ํญ FFE ๋ฐ ์ญํ์ T-์ฝ์ผ์ ์ฌ์ฉํ๋ ์ ๋ ฅ ํจ์จ์ ์ธ PAM-4 VCSEL ์ก์ ๊ธฐ๋ฅผ ์ ์ํ๋ค. ์์ ๋ณด๊ฐ๊ธฐ(PI)๋ ๋ถ๋ถ ๊ฐ๊ฒฉ FFE ํญ์ ์์ฑํ๊ณ 4-์์ ํด๋ญ ์ค๋ฅ๋ฅผ ์์ ํ๋ ๋ฐ ์ฌ์ฉ๋๋ค. ์ง๋ ฌํ ์ ๋ ฅ ์๋น๋ฅผ ์ค์ด๊ธฐ ์ํด ์ถ๋ ฅ ๋๋ผ์ด๋ฒ์์ MSB์ LSB๋ฅผ ๋ ๊ฐ์ 4:1 MUX๋ฅผ ํตํด ๊ฒฐํฉํ๋ ๋์ 8:1 MUX๋ฅผ ํตํด PAM-4๋ก ๊ฒฐํฉํ๋ ํ๋ก๊ฐ ์ ์๋๋ค. ๋ด๋ถ ๋ฐ ์ถ๋ ฅ ๋
ธ๋์์ T-์ฝ์ผ์ ๋์ญํญ์ ์ฆ๊ฐ์ํค๊ณ ๊ธฐํธ ๊ฐ ๊ฐ์ญ(ISI)์ ์ ๊ฑฐํ๋ค. ์ถ๋ ฅ ๋คํธ์ํฌ์์ ์ญํ์ T-์ฝ์ผ์ T-์ฝ์ผ์ด ์๋ ๊ฒฝ์ฐ๋ณด๋ค ๋์ญํญ์ 1.61๋ฐฐ ์ฆ๊ฐ์ํจ๋ค. VCSEL ๋๋ผ์ด๋ฒ๋ ์๊ทน ๊ตฌ๋ ๋ฐ ์ ๋ ฅ ๊ฐ์๋ฅผ ์ํด ๋์ VSS ๋๋ฉ์ธ์ ๋ฐฐ์น๋๋ค. ์ด ์นฉ์ 40 nm CMOS ๊ธฐ์ ๋ก ์ ์๋์๋ค. ์ ์๋ VCSEL ์ก์ ๊ธฐ๋ ๊ฐ๊ฐ 3.03pJ/b์ 2.09pJ/b์ ์ ๋ ฅ ํจ์จ๋ก ์ต๋ 48Gb/s NRZ์ 64Gb/s PAM-4๊น์ง ์๋ํ๋ค.ABSTRACT I
CONTENTS III
LIST OF FIGURES V
LIST OF TABLES IX
CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 5
CHAPTER 2 BACKGROUND OF HIGH-SPEED INTERFACE 6
2.1 OVERVIEW 6
2.2 BASIS OF DATA CENTER ARCHITECTURE 9
2.3 SHORT-REACH INTERFACE STANDARDS 12
2.4 ANALYSES OF BANDWIDTH EXTENSION TECHNIQUES 16
2.4.1 FRACTIONALLY-SPACED FFE 16
2.4.2 TRANSMISSION LINE 21
2.4.3 INDUCTOR 24
2.4.4 T-COIL 33
CHAPTER 3 DESIGN OF 48 GB/S PAM-4 ELECTRICAL TRANSMITTER IN 65 NM CMOS 43
3.1 OVERVIEW 43
3.2 FFE BASED ON DOUBLE-SHIELDED COPLANAR WAVEGUIDE 46
3.2.1 BASIC CONCEPT 46
3.2.2 PROPOSED DOUBLE-SHIELDED COPLANAR WAVEGUIDE 47
3.3 DESIGN CONSIDERATION ON 4:1 MUX 50
3.4 PROPOSED PAM-4 ELECTRICAL TRANSMITTER 53
3.5 MEASUREMENT 57
CHAPTER 4 DESIGN OF 64 GB/S PAM-4 OPTICAL TRANSMITTER IN 40 NM CMOS 64
4.1 OVERVIEW 64
4.2 DESIGN CONSIDERATION OF OPTICAL TRANSMITTER 66
4.3 PROPOSED PAM-4 VCSEL TRANSMITTER 69
4.4 MEASUREMENT 82
CHAPTER 5 CONCLUSIONS 88
BIBLIOGRAPHY 90
์ด ๋ก 101๋ฐ
A 2-40 Gb/s PAM4/NRZ dual-mode wireline transmitter with 4:1 MUX in 65-nm CMOS
This paper presents a 2-40 Gb/s dual-mode wireline transmitter supporting the four-level pulse amplitude modulation (PAM4) and non-return-to-zero (NRZ) modulation with a multiplexer (MUX)-based two-tap feed-forward equalizer (FFE). An edge-acceleration technique is proposed for the 4:1 MUX to increase the bandwidth. By utilizing a dedicated cascode current source, the output swing can achieve 900 mV with a level deviation of only 0.12% for PAM4. Fabricated in a 65-nm CMOS process, the transmitter consumes 117 mW and 89 mW at 40 Gb/s in PAM4 and NRZ at 1.2 V supply. ยฉ 2018, Institute of Electronics Engineers of Korea. All rights reserved
High Speed Reconfigurable NRZ/PAM4 Transceiver Design Techniques
While the majority of wireline standards use simple binary non-return-to-zero (NRZ) signaling, four-level pulse-amplitude modulation (PAM4) standards are emerging to increase bandwidth density. This dissertation proposes efficient implementations for high speed NRZ/PAM4 transceivers. The first prototype includes a dual-mode NRZ/PAM4 serial I/O transmitter which can support both modulations with minimum power and hardware overhead. A source-series-terminated (SST) transmitter achieves 1.2Vpp output swing and employs lookup table (LUT) control of a 31-segment output digital-to-analog converter (DAC) to implement 4/2-tap feed-forward equalization (FFE) in NRZ/PAM4 modes, respectively. Transmitter power is improved with low-overhead analog impedance control in the DAC cells and a quarter-rate serializer based on a tri-state inverter-based mux with dynamic pre-driver gates. The transmitter is designed to work with a receiver that implements an NRZ/PAM4 decision feedback equalizer (DFE) that employs 1 finite impulse response (FIR) and 2 infinite impulse response (IIR) taps for first post-cursor and long-tail ISI cancellation, respectively. Fabricated in GP 65-nm CMOS, the transmitter occupies 0.060mmยฒ area and achieves 16Gb/s NRZ and 32Gb/s PAM4 operation at 10.4 and 4.9 mW/Gb/s while operating over channels with 27.6 and 13.5dB loss at Nyquist, respectively. The second prototype presents a 56Gb/s four-level pulse amplitude modulation (PAM4) quarter-rate wireline receiver which is implemented in a 65nm CMOS process. The frontend utilize a single stage continuous time linear equalizer (CTLE) to boost the main cursor and relax the pre-cursor cancelation requirement, requiring only a 2-tap pre-cursor feed-forward equalization (FFE) on the transmitter side. A 2-tap decision feedback equalizer (DFE) with one finite impulse response (FIR) tap and one infinite impulse response (IIR) tap is employed to cancel first post-cursor and longtail inter-symbol interference (ISI). The FIR tap direct feedback is implemented inside the CML slicers to relax the critical timing of DFE and maximize the achievable data-rate. In addition to the per-slice main 3 data samplers, an error sampler is utilized for background threshold control and an edge-based sampler performs both PLL-based CDR phase detection and generates information for background DFE tap adaptation. The receiver consumes 4.63mW/Gb/s and compensates for up to 20.8dB loss when operated with a 2- tap FFE transmitter. The experimental results and comparison with state-of-the-art shows superior power efficiency of the presented prototypes for similar data-rate and channel loss. The usage of proposed design techniques are not limited to these specific prototypes and can be applied for any wireline transceiver with different modulation, data-rate and CMOS technology
Design of Low-Power NRZ/PAM-4 Wireline Transmitters
Rapid growing demand for instant multimedia access in a myriad of digital devices has pushed
the need for higher bandwidth in modern communication hardwares ranging from short-reach (SR)
memory/storage interfaces to long-reach (LR) data center Ethernets. At the same time, comprehensive
design optimization of link system that meets the energy-efficiency is required for mobile
computing and low operational cost at datacenters. This doctoral study consists of design of two
low-swing wireline transmitters featuring a low-power clock distribution and 2-tap equalization in
energy-efficient manners up to 20-Gb/s operation. In spite of the reduced signaling power in the
voltage-mode (VM) transmit driver, the presence of the segment selection logic still diminishes the
power saving benefit.
The first work presents a scalable VM transmitter which offers low static power dissipation
and adopts an impedance-modulated 2-tap equalizer with analog tap control, thereby obviating
driver segmentation and reducing pre-driver complexity and dynamic power. Per-channel quadrature
clock generation with injection-locked oscillators (ILO) allows the generation of rail-to-rail
quadrature clocks. Energy efficiency is further improved with capacitively driven low-swing global
clock distribution and supply scaling at lower data rates, while output eye quality is maintained at
low voltages with automatic phase calibration of the local ILO-generated quarter-rate clocks. A
prototype fabricated in a general purpose 65 nm CMOS process includes a 2 mm global clock
distribution network and two transmitters that support an output swing range of 100-300mV with
up to 12-dB of equalization. The transmitters achieve 8-16 Gb/s operation at 0.65-1.05 pJ/b energy
efficiency.
The second work involves a dual-mode NRZ/PAM-4 differential low-swing voltage-mode (VM)
transmitter. The pulse-selected output multiplexing allows reduction of power supply and deterministic
jitter caused by large on-chip parasitic inherent in the transmission-gate-based multiplexers
in the earlier work. Analog impedance control replica circuits running in the background produce
gate-biasing voltages that control the peaking ratio for 2-tap feed-forward equalization and
PAM-4 symbol levels for high-linearity. This analog control also allows for efficient generation of
the middle levels in PAM-4 operation with good linearity quantified by level separation mismatch
ratio of 95%. In NRZ mode, 2-tap feedforward equalization is configurable in high-performance
controlled-impedance or energy-efficient impedance-modulated settings to provide performance
scalability. Analytic design consideration on dynamic power, data-rate, mismatch, and output
swing brings optimal performance metric on the given technology node. The proof-of-concept
prototype is verified on silicon with 65 nm CMOS process with improved performance in speed
and energy-efficiency owing to double-stack NMOS transistors in the output stage. The transmitter consumes as low as 29.6mW in 20-Gb/s NRZ and 25.5mW in the 28-Gb/s PAM-4 operations
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Design of Energy-Efficient Equalization and Data Encoding/Decoding Techniques for Wireline Communication Systems
Ever increasing global internet data tra๏ฌc has driven up the demand for cutting-edge high-speed wireline communication systems including SerDes PHY for various interfaces, interconnects, data centers servers and switches in optical systems. Operating wireline communications at higher data rates leads to signals su๏ฌering from greater channel loss and exponential increase in power consumption, mainly caused by a heavier amount of required equalization.
In this dissertation, two distinct methodologies for designing SerDes transceivers are presented: 1) a pulse width modulated (PWM) time-domain feed forward equalizer (FFE) and linearity improvement technique for higher-order pulse amplitude modulation (PAM) including PAM-8, and 2) an inter-symbol interference (ISI)-resilient data encoding and decoding technique with Dicode encoding and error correction logic for low-bandwidth wireline channels, as an alternative strategy for communicating in an energy-e๏ฌcient way on bandwidth-limited wireline channels without using conventional equalizers or ๏ฌlters.
The ๏ฌrst topic is a PAM-8 wireline transceiver with receiver-side pulse-width-modulated (PWM) or time-domain based feed forward equalization (FFE) technique. The receiver converts voltage-modulated signals or PAM signals to PWM signals and processes them using inverter based delay elements having rail to rail voltage swing. Time-to-voltage and voltage-to-time converters are designed to have non-linearity with opposite signs with the aim of achieving higher front-end linearity on the receiver. The proposed PAM-8 transceiver can operate from 12.0 Gb/s to 39.6 Gb/s and compensates 14 dB loss at 6.6 GHz with an e๏ฌciency of 8.66 pJ/bit in 65 nm CMOS.
The second topic is an alternative strategy for communicating on bandwidth-limited wireline channels without using conventional equalizers or ๏ฌlters (FFE, DFE, and CTLE): Inter-symbol interference (ISI) resilient Dicode encoding and error correction for low-bandwidth wireline channels. The key observation is that Dicode-encoded data have no consecutive 1s or -1s. With this known information, the error correction logic at the receiver can correct multi-bit errors due to ISI. Implemented in 65 nm CMOS, the proposed digital encoding and decoding approach can achieve BER less than 10โ12 while communicating on a channel with an insertion loss of 24.2 dB and 21.4 dB with 2.56 pJ/bit and 2.66 pJ/bit e๏ฌciency while operating at 13.6 Gb/s and 16 Gb/s, respectively
70 Gb/s low-power DC-coupled NRZ differential electro-absorption modulator driver in 55 nm SiGe BiCMOS
We present a 70 Gb/s capable optical transmitter consisting of a 50 mu m long GeSi electro-absorption modulator (integrated in silicon photonics) and a fully differential driver designed in a 55 nm SiGe BiCMOS technology. By properly unbalancing the output stage, the driver can be dc-coupled to the modulator thus avoiding the use of on-chip or external bias-Ts. At a wavelength of 1560 nm, open eye diagrams for 70 Gb/s after transmission over 2 km standard single-mode fiber were demonstrated. The total power consumption is 61 mW, corresponding to 0.87 pJ/b at 70 Gb/s. Bit-error rate measurements at 50 Gb/s and 56 Gb/s (performed both back to back and with up to 2 km standard single-mode fiber) demonstrate large (0.4 UI at a BER of 10(-12)) horizontal eye margins. This optical transmitter is ideally suited for datacenter applications that require densely integrated transceivers with a low power consumption
Design of High-Speed SerDes Transceiver for Chip-to-Chip Communications in CMOS Process
With the continuous increase of on-chip computation capacities and exponential growth of data-intensive applications, the high-speed data transmission through serial links has become the backbone for modern communication systems. To satisfy the massive data-exchanging requirement, the data rate of such serial links has been updated from several Gb/s to tens of Gb/s. Currently, the commercial standards such as Ethernet 400GbE, InfiniBand high data rate (HDR), and common electrical interface (CEI)-56G has been developing towards 40+ Gb/s. As the core component within these links, the transceiver chipset plays a fundamental role in balancing the operation speed, power consumption, area occupation, and operation range. Meanwhile, the CMOS process has become the dominant technology in modern transceiver chip fabrications due to its large-scale digital integration capability and aggressive pricing advantage. This research aims to explore advanced techniques that are capable of exploiting the maximum operation speed of the CMOS process, and hence provides potential solutions for 40+ Gb/s CMOS transceiver designs. The major contributions are summarized as follows.
A low jitter ring-oscillator-based injection-locked clock multiplier (RILCM) with a hybrid frequency tracking loop that consists of a traditional phase-locked loop (PLL), a timing-adjusted loop, and a loop selection state-machine is implemented in 65-nm C-MOS process. In the ring voltage-controlled oscillator, a full-swing pseudo-differential delay cell is proposed to lower the device noise to phase noise conversion. To obtain high operation speed and high detection accuracy, a compact timing-adjusted phase detector tightly combined with a well-matched charge pump is designed. Meanwhile, a lock-loss detection and lock recovery is devised to endow the RILCM with a similar lock-acquisition ability as conventional PLL, thus excluding the initial frequency set- I up aid and preventing the potential lock-loss risk. The experimental results show that the figure-of-merit of the designed RILCM reaches -247.3 dB, which is better than previous RILCMs and even comparable to the large-area LC-ILCMs.
The transmitter (TX) and receiver (RX) chips are separately designed and fab- ricated in 65-nm CMOS process. The transmitter chip employs a quarter-rate multi-multiplexer (MUX)-based 4-tap feed-forward equalizer (FFE) to pre-distort the output. To increase the maximum operating speed, a bandwidth-enhanced 4:1 MUX with the capability of eliminating charge-sharing effect is proposed. To produce the quarter-rate parallel data streams with appropriate delays, a compact latch array associated with an interleaved-retiming technique is designed. The receiver chip employs a two-stage continuous-time linear equalizer (CTLE) as the analog front-end and integrates an improved clock data recovery to extract the sampling clocks and retime the incoming data. To automatically balance the jitter tracking and jitter suppression, passive low-pass filters with adaptively-adjusted bandwidth are introduced into the data-sampling path. To optimize the linearity of the phase interpolation, a time-averaging-based compensating phase interpolator is proposed. For equalization, a combined TX-FFE and RX-CTLE is applied to compensate for the channel loss, where a low-cost edge-data correlation-based sign zero-forcing adaptation algorithm is proposed to automatically adjust the TX-FFEโs tap weights. Measurement results show that the fabricated transmitter/receiver chipset can deliver 40 Gb/s random data at a bit error rate of 16 dB loss at the half-baud frequency, while consuming a total power of 370 mW
Modeling and Design of High-Speed CMOS Receivers for Short-Reach Photonic Links
This dissertation presents several research outcomes towards designing high-speed CMOS optical receivers for energy-efficient short-reach optical links. First, it provides a wide survey of recently published equalizer-based receivers and presents a novel methodology to accurately calculate their noise. The proposed methodology is then used to find the receiver that achieves the best sensitivity.
Second, the trade-off between sensitivity and power dissipation of the receiver is optimized to reduce the energy consumption per bit of the overall link. Design trade-offs for the receiver, transmitter, and the overall link are presented, and comparisons are made to study how much receiver sensitivity can be sacrificed to save its power dissipation before this power reduction is outpaced by the transmitterโs increase in power. Unlike conventional wisdom, our results show that energy-efficient links require low-power receivers with input capacitance much smaller than that required for noise-optimum performance.
Third, the thesis presents a novel equalization technique for optical receivers. A linear equalizer (LE) is realized by adding a pole in the feedback paths of an active feedback-based wideband amplifier. By embedding the peaking in the main amplifier (MA), the front-end meets the sensitivity and gain of conventional LE-based receivers with better energy efficiency by eliminating the standalone equalizer stage(s). Electrical measurements are presented to demonstrate the capability of the proposed technique in restoring the bandwidth and improving the performance over the conventional design
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Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (โค10 ๏ฟฝm)
Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (โค100 ๏ฟฝm) using fine-pitch (โค10 ๏ฟฝm) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 ๏ฟฝm pitch interconnects with a low specific contact resistance of โค0.7 โฆ-๏ฟฝm2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (โค500 ๏ฟฝm) with low loss (โค2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (โค0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology