Kecerdasan matematik-logik dalam kalangan pelajar sarjana Pendidikan Teknik dan Vokasional UTHM

Kecerdasan matematik-logik sering dikaitkan dengan penguasaan pelajar dalam subjek matematik. Pencapaian pelajar, khususnya pelajar Sarjana Pendidikan Teknik dan Vokasional, Universiti Tun Hussein Onn Malaysia (UTHM) dalam kursus Statistik dalam Penyelidikan sedikit sebanyak mempengaruhi pencapaian akademik pelajar. Oleh itu, kajian ini dijalankan untuk mengkaji pengaruh kecerdasan matematik-logik terhadap pencapaian pelajar dalam kursus Statistik dalam Penyelidikan. Kajian berbentuk tinjauan secara kuantitatif untuk melihat hubungan diantara dua pembolehubah iaitu pembolehubah tidak bersandar (kecerdasan matematik-logik) dan pembolehubah bersandar (penguasaan pelajar dalam kursus Statistik dalam Penyelidikan). Persampelan rawak mudah digunakan dalam kajian ini dengan mengambil sampel seramai 108 orang pelajar Sarjana Pendidikan Teknik dan Vokasional sebagai responden kajian. Data diperoleh daripada sampel dengan menggunakan borang soal selidik yang diolah berdasarkan alat pengukuran kecerdasan MIDAS (Multiple Intelligence Development Assessment Scales). Data dianalisis menggunakan perisian SPSS (Statistical Package for Social Science) versi 16.0 yang melibatkan ujian statistik skor min dan kolerasi pangkat Spearman. Hasil dapatan kajian menunjukkan tahap kecenderungan kecerdasan matematik-logik pelajar berada pada tahap yang tinggi dan mempunyai hubungan yang signifikan dengan pencapaian pelajar dalam kursus Statistik dalam Penyelidikan. Berdasarkan dapatan kajian boleh disimpulkan bahawa kecerdasan matematik-logik dapat dijadikan kayu ukur dalam memastikan kejayaan pelajar

Diseño e implementación de un microprocesador de propósito específico

Este documento pretende compartir la experiencia del diseño de un procesador y su implementación en una FPGA (Spartan 3E – 100E), mostrando las características generales que debe tener el procesador para que sea lo suficientemente flexible, y que herramientas adicionales se deben crear para facilitar sus pruebas e implementación

Diseño e implementación de un microprocesador de propósito específico

Este documento pretende compartir la experiencia del diseño de un procesador y su implementación en una FPGA (Spartan 3E – 100E), mostrando las características generales que debe tener el procesador para que sea lo suficientemente flexible, y que herramientas adicionales se deben crear para facilitar sus pruebas e implementación

Towards Software-Defined Data Protection: GDPR Compliance at the Storage Layer is Within Reach

Enforcing data protection and privacy rules within large data processing applications is becoming increasingly important, especially in the light of GDPR and similar regulatory frameworks. Most modern data processing happens on top of a distributed storage layer, and securing this layer against accidental or malicious misuse is crucial to ensuring global privacy guarantees. However, the performance overhead and the additional complexity for this is often assumed to be significant -- in this work we describe a path forward that tackles both challenges. We propose "Software-Defined Data Protection" (SDP), an adoption of the "Software-Defined Storage" approach to non-performance aspects: a trusted controller translates company and application-specific policies to a set of rules deployed on the storage nodes. These, in turn, apply the rules at line-rate but do not take any decisions on their own. Such an approach decouples often changing policies from request-level enforcement and allows storage nodes to implement the latter more efficiently. Even though in-storage processing brings challenges, mainly because it can jeopardize line-rate processing, we argue that today's Smart Storage solutions can already implement the required functionality, thanks to the separation of concerns introduced by SDP. We highlight the challenges that remain, especially that of trusting the storage nodes. These need to be tackled before we can reach widespread adoption in cloud environments

The hardware implementation of a high performance AES based on inner pipeline

为了提升AES的性能,本文采用轮内流水线技术进行AES硬件设计。在对AES轮单元复杂的字节代换/逆字节代换、列变换/逆列变换进行了算法分析的基础上,进行了AES轮单元的轮内7级流水线设计。特别是采用常数矩阵乘积形式和复用列变换进行了逆列变换设计,降低了硬件资源的占用。采用XIlInX ISE10.1工具进行了各个型号fPgA的硬件实现,实验数据表明文中提出的硬件实现方案提升了AES的数据吞吐率与吞吐率/面积比。Abtract: An inner pipelined hardware design of AES is presented in this paper for the performance improvement of AES.Based on the algorithmic analysis of the SubBytes/invSubBytes and MixColumns/invMixColumns, a 7-stage pipelined structure, which applies the invMixColumns design to the multiplexing MixColumns and adopts the form of arithmetic product of constant matrix, is proposed to reduce the cost of the hardware resources.The implementation of the proposed is carried out in several FPGAs using the Xilinx ISE10.1and the results have shown an improvement in thedatathroughoutratioand theratioofdatathroughoutand area

ControlFreak: Signature Chaining to Counter Control Flow Attacks

Abstract: Many modern embedded systems use networks to communicate. This increases the attack surface: the adversary does not need to have physical access to the system and can launch remote attacks. By exploiting software bugs, the attacker might be able to change the behavior of a program. Security violations in safety-critical systems are particularly dangerous since they might lead to catastrophic results. Hence, safety-critical software requires additional protection. We present an approach to detect and prevent control flow attacks. Such attacks maliciously modify program's control flow to achieve the desired behavior. We develop ControlFreak, a hardware watchdog to monitor program execution and to prevent illegal control flow transitions. The watchdog employs chained signatures to detect any modification of the instruction stream and any illegal jump in the program even if signatures are maliciously modified