A Novel High Linearity and Low Power Folded CMOS LNA for UWB Receivers

© 2017 World Scientific Publishing Company. Electronic version of an article published as Journal of Circuits, Systems and Computers, Vol. 27, No. 03, 1850047, https://doi.org/10.1142/S0218126618500470.This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18μm CMOS technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8dB. The input and output reflection coefficients both are lower than -10.0dB over 2.5~11.5GHz. The input third-order intercept point (IIP3) is 5.6dBm at 8GHz and the noise figure (NF) is lower than 4.0dB. The LNA consumes 5.4mW power under a 1V supply voltage.Peer reviewe

A Review of CMOS Low Noise Amplifier for UWB System

A number of CMOS low noise amplifier (LNA) design for ultra-wideband (UWB) application had been produced with a various topology and techniques from year 2004 to 2016. The performance of LNA such as frequency bandwidth, noise figure, input and output matching and gain depend with the choice of the topology and technique used. Among the techniques introduced are current reuse, common source, resistive feedback, common gate, Chebyshev filter, distributed amplifier, folded cascade and negative feedback. This paper presents the collection of review about design of low noise amplifier used for UWB application in term of topology circuit. Thus, the problem and limitation of the CMOS LNA for UWB application are reviewed. Furthermore, recent developments of CMOS LNAs are examined and a comparison of the performance criteria of various topologies is presented

Characterization of 28 nm FDSOI MOS and application to the design of a low-power 2.4 GHz LNA

IoT is expected to connect billions of devices all over world in the next years, and in a near future, it is expected to use LR-WPAN in a wide variety of applications. Not all the devices will require of high performance but will require of low power hungry systems since most of them will be powered with a battery. Conventional CMOS technologies cannot cover these needs even scaling it to very small regimes, which appear other problems. Hence, new technologies are emerging to cover the needs of this devices. One promising technology is the UTBB FDSOI, which achieves good performance with very good energy efficiency. This project characterizes this technology to obtain a set of parameters of interest for analog/RF design. Finally, with the help of a low-power design methodology (gm/Id approach), a design of an ULP ULV LNA is performed to check the suitability of this technology for IoT

High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works

ULTRA LOW POWER FSK RECEIVER AND RF ENERGY HARVESTER

This thesis focuses on low power receiver design and energy harvesting techniques as methods for intelligently managing energy usage and energy sources. The goal is to build an inexhaustibly powered communication system that can be widely applied, such as through wireless sensor networks (WSNs). Low power circuit design and smart power management are techniques that are often used to extend the lifetime of such mobile devices. Both methods are utilized here to optimize power usage and sources. RF energy is a promising ambient energy source that is widely available in urban areas and which we investigate in detail. A harvester circuit is modeled and analyzed in detail at low power input. Based on the circuit analysis, a design procedure is given for a narrowband energy harvester. The antenna and harvester co-design methodology improves RF to DC energy conversion efficiency. The strategy of co-design of the antenna and the harvester creates opportunities to optimize the system power conversion efficiency. Previous surveys have found that ambient RF energy is spread broadly over the frequency domain; however, here it is demonstrated that it is theoretically impossible to harvest RF energy over a wide frequency band if the ambient RF energy source(s) are weak, owing to the voltage requirements. It is found that most of the ambient RF energy lies in a series of narrow bands. Two different versions of harvesters have been designed, fabricated, and tested. The simulated and measured results demonstrate a dual-band energy harvester that obtains over 9% efficiency for two different bands (900MHz and 1800MHz) at an input power as low as -19dBm. The DC output voltage of this harvester is over 1V, which can be used to recharge the battery to form an inexhaustibly powered communication system. A new phase locked loop based receiver architecture is developed to avoid the significant conversion losses associated with OOK architectures. This also helps to minimize power consumption. A new low power mixer circuit has also been designed, and a detailed analysis is provided. Based on the mixer, a low power phase locked loop (PLL) based receiver has been designed, fabricated and measured. A power management circuit and a low power transceiver system have also been co-designed to provide a system on chip solution. The low power voltage regulator is designed to handle a variety of battery voltage, environmental temperature, and load conditions. The whole system can work with a battery and an application specific integrated circuit (ASIC) as a sensor node of a WSN network

A New Application of Current Conveyors: The Design of Wideband Controllable Low-Noise Amplifiers

The aim of this paper is three-fold. First, it reviews the low-noise amplifier and its relevance in wireless communications receivers. Then it presents an exhaustive review of the existing topologies. Finally, it introduces a new class of LNAs, based on current conveyors, describing the founding principle and the performances of a new single-ended LNA. The new LNAs offer the following notable advantages: total absence of passive elements (and the smallest LNAs in their respective classes); wideband performance, with stable frequency responses from 0 to 3 GHz; easy gain control over wide ranges (0 to 20 dB). Comparisons with other topologies prove that the new class of LNA greatly advances the state of the art

Design of low power CMOS UWB transceiver ICs

Master'sMASTER OF ENGINEERIN

CMOS radio frequency circuits for short-range direct-conversion receivers

The research described in this thesis is focused on the design and implementation of radio frequency (RF) circuits for direct-conversion receivers. The main interest is in RF front-end circuits, which contain low-noise amplifiers, downconversion mixers, and quadrature local oscillator signal generation circuits. Three RF front-end circuits were fabricated in a short-channel CMOS process and experimental results are presented. A low-noise amplifier (LNA) is typically the first amplifying block in the receiver. A large number of LNAs have been reported in the literature. In this thesis, wideband LNA structures are of particular interest. The most common and relevant LNA topologies are analyzed in detail in the frequency domain and theoretical limitations are found. New LNA structures are presented and a comparison to the ones found in the literature is made. In this work, LNAs are implemented with downconversion mixers as RF front-ends. The designed mixers are based on the commonly used Gilbert cell. Different mixer implementation alternatives are presented and the design of the interface between the LNA and the downconversion mixer is discussed. In this work, the quadrature local oscillator signal is generated either by using frequency dividers or polyphase filters (PPF). Different possibilities for implementing frequency dividers are briefly described. Polyphase filters were already introduced by the 1970s and integrated circuit (IC) realizations to generate quadrature signals have been published since the mid-1990s. Although several publications where the performance of the PPFs has been studied either by theoretical calculations or simulations can be found in the literature, none of them covers all the relevant design parameters. In this thesis, the theory behind the PPFs is developed such that all the relevant design parameters needed in the practical circuit design have been calculated and presented with closed-form equations whenever possible. Although the main focus was on twoand three-stage PPFs, which are the most common ones encountered in practical ICs, the presented calculation methods can be extended to analyze the performance of multistage PPFs as well. The main application targets of the circuits presented in this thesis are the short-range wireless sensor system and ultrawideband (UWB). Sensors are capable of monitoring temperature, pressure, humidity, or acceleration, for example. The amount of transferred data is typically small and therefore a modest bit rate, less than 1 Mbps, is adequate. The sensor system applied in this thesis operates at 2.4-GHz ISM band (Industrial, Scientific, and Medical). Since the sensors must be able to operate independently for several years, extremely low power consumption is required. In sensor radios, the receiver current consumption is dominated by the blocks and elements operating at the RF. Therefore, the target was to develop circuits that can offer satisfactory performance with a current consumption level that is small compared to other receivers targeted for common cellular systems. On the other hand, there is a growing need for applications that can offer an extremely high data rate. UWB is one example of such a system. At the moment, it can offer data rates of up to 480 Mbps. There is a frequency spectrum allocated for UWB systems between 3.1 and 10.6 GHz. The UWB band is further divided into several narrower band groups (BG), each occupying a bandwidth of approximately 1.6 GHz. In this work, a direct-conversion RF front-end is designed for a dual-band UWB receiver, which operates in band groups BG1 and BG3, i.e. at 3.1 – 4.8 GHz and 6.3 – 7.9 GHz frequency areas, respectively. Clearly, an extremely wide bandwidth combined with a high operational frequency poses challenges for circuit design. The operational bandwidths and the interfaces between the circuit blocks need to be optimized to cover the wanted frequency areas. In addition, the wideband functionality should be achieved without using a number of on-chip inductors in order to minimize the die area, and yet the power consumption should be kept as small as possible. The characteristics of the two main target applications are quite different from each other with regard to power consumption, bandwidth, and operational frequency requirements. A common factor for both is their short, i.e. less than 10 meters, range. Although the circuits presented in this thesis are targeted on the two main applications mentioned above, they can be utilized in other kind of wireless communication systems as well. The performance of three experimental circuits was verified with measurements and the results are presented in this work. Two of them have been a part of a whole receiver including baseband amplifiers and filters and analog-to-digital converters. Experimental circuits were fabricated in a 0.13-µm CMOS process. In addition, this thesis includes design examples where new circuit ideas and implementation possibilities are introduced by using 0.13-µm and 65-nm CMOS processes. Furthermore, part of the theory presented in this thesis is validated with design examples in which actual IC component models are used.Tässä väitöskirjassa esitetty tutkimus keskittyy suoramuunnosvastaanottimen radiotaajuudella (radio frequency, RF) toimivien piirien suunnitteluun ja toteuttamiseen. Työ keskittyy vähäkohinaiseen vahvistimeen (low-noise amplifier, LNA), alassekoittajaan ja kvadratuurisen paikallisoskillaattorisignaalin tuottavaan piiriin. Työssä toteutettiin kolme RF-etupäätä erittäin kapean viivanleveyden CMOS-prosessilla, ja niiden kokeelliset tulokset esitetään. Vähäkohinainen vahvistin on yleensä ensimmäinen vahvistava lohko vastaanottimessa. Useita erilaisia vähäkohinaisia vahvistimia on esitetty kirjallisuudessa. Tämän työn kohteena ovat eritoten laajakaistaiset LNA-rakenteet. Tässä työssä analysoidaan taajuustasossa yleisimmät ja oleellisimmat LNA-topologiat. Lisäksi uusia LNA-rakenteita on esitetty tässä työssä ja niitä on verrattu muihin kirjallisuudessa esitettyihin piireihin. Tässä työssä LNA:t on toteutettu yhdessä alassekoittimen kanssa muodostaen RF-etupään. Työssä suunnitellut alassekoittimet perustuvat yleisesti käytettyyn Gilbertin soluun. Erilaisia sekoittajan suunnitteluvaihtoehtoja ja LNA:n ja alassekoittimen välisen rajapinnan toteutustapoja on esitetty. Tässä työssä kvadratuurinen paikallisoskillaattorisignaali on muodostettu joko käyttämällä taajuusjakajia tai monivaihesuodattimia. Erilaisia taajuusjakajia ja niiden toteutustapoja käsitellään yleisellä tasolla. Monivaihesuodatinta, joka on alunperin kehitetty jo 1970-luvulla, on käytetty integroiduissa piireissä kvadratuurisignaalin tuottamiseen 1990-luvun puolivälistä lähtien. Kirjallisuudesta löytyy lukuisia artikkeleita, joissa monivaihesuodattimen toimintaa on käsitelty teoreettisesti laskien ja simuloinnein. Kuitenkaan kaikkia sen suunnitteluparametreja ei tähän mennessä ole käsitelty. Tässä työssä monivaihesuodattimen teoriaa on kehitetty edelleen siten, että käytännön piirisuunnittelussa tarvittavat oleelliset parametrit on analysoitu ja suunnitteluyhtälöt on esitetty suljetussa muodossa aina kuin mahdollista. Vaikka työssä on keskitytty yleisimpiin eli kaksi- ja kolmiasteisiin monivaihesuodattimiin, on työssä esitetty menetelmät, joilla laskentaa voidaan jatkaa aina useampiasteisiin suodattimiin asti. Työssä esiteltyjen piirien pääkohteina ovat lyhyen kantaman sensoriradio ja erittäin laajakaistainen järjestelmä (ultrawideband, UWB). Sensoreilla voidaan tarkkailla esimerkiksi ympäristön lämpötilaa, kosteutta, painetta tai kiihtyvyyttä. Siirrettävän tiedon määrä on tyypillisesti vähäistä, jolloin pieni tiedonsiirtonopeus, alle 1 megabitti sekunnissa, on välttävä. Tämän työn kohteena oleva sensoriradiojärjestelmä toimii kapealla kaistalla 2,4 gigahertsin ISM-taajuusalueella (Industrial, Scientific, and Medical). Koska sensorien tavoitteena on toimia itsenäisesti ilman pariston vaihtoa useita vuosia, täytyy niiden kuluttaman virran olla erittäin vähäistä. Sensoriradiossa vastaanottimen tehonkulutuksen kannalta määräävässä asemassa ovat radiotaajuudella toimivat piirit. Tavoitteena oli tutkia ja kehittää piirirakenteita, joilla päästään tyydyttävään suorituskykyyn tehonkulutuksella, joka on vähäinen verrattuna muiden tavallisten langattomien tiedonsiirtojärjestelmien radiovastaanottimiin. Toisaalta viime aikoina on kasvanut tarvetta myös järjestelmille, jotka kykenevät tarjoamaan erittäin korkean tiedonsiirtonopeuden. UWB on esimerkki tällaisesta järjestelmästä. Tällä hetkellä se tarjoaa tiedonsiirtonopeuksia aina 480 megabittiin sekunnissa. UWB:lle on varattu taajuusalueita 3,1 ja 10,6 gigahertsin taajuuksien välillä. Kyseinen kaista on edelleen jaettu pienempiin taajuusryhmiin (band group, BG), joiden kaistanleveys on noin 1,6 gigahertsiä. Tässä työssä on toteutettu RF-etupää radiovastaanottimeen, joka pystyy toimimaan BG1:llä ja BG3:lla eli taajuusalueilla 3,1 - 4,7 GHz ja 6,3 - 7,9 GHz. Erittäin suuri kaistanleveys yhdistettynä korkeaan toimintataajuuteen tekee radiotaajuuspiirien suunnittelusta haasteellista. Piirirakenteiden toimintakaistat ja piirien väliset rajapinnat tulee optimoida riittävän laajoiksi käyttämättä kuitenkaan liian montaa piille integroitua kelaa piirin pinta-alan minimoimiseksi, ja lisäksi piirit tulisi toteuttaa mahdollisimman alhaisella tehonkulutuksella. Työssä esiteltyjen piirien kaksi pääkohdetta ovat hyvin erityyppisiä, mitä tulee tehonkulutus-, kaistanleveys- ja toimintataajuusvaatimuksiin. Yhteistä molemmille on lyhyt, alle 10 metrin kantama. Vaikka tässä työssä esitellyt piirit onkin kohdennettu kahteen pääsovelluskohteeseen, voidaan esitettyjä piirejä käyttää myös muiden tiedonsiirtojärjestelmien piirien suunnitteluun. Tässä työssä esitetään mittaustuloksineen yhteensä kolme kokeellista piiriä yllämainittuihin järjestelmiin. Kaksi ensimmäistä kokeellista piiriä muodostaa kokonaisen radiovastaanottimen yhdessä analogisten kantataajuusosien ja analogia-digitaali-muuntimien kanssa. Esitetyt kokeelliset piirit on toteutettu käyttäen 0,13 µm:n viivanleveyden CMOS-tekniikkaa. Näiden lisäksi työ pitää sisällään piirisuunnitteluesimerkkejä, joissa esitetään ideoita ja mahdollisuuksia käyttäen 0,13 µm:n ja 65 nm:n viivanleveyden omaavia CMOS-tekniikoita. Lisäksi piirisuunnitteluesimerkein havainnollistetaan työssä esitetyn teorian paikkansapitävyyttä käyttämällä oikeita komponenttimalleja.reviewe

Design of broadband inductor-less RF front-ends with high dynamic range for G.hn

System-on-Chip (SoC) was adopted in recent years as one of the solutions to reduce the cost of integrated systems. When the SoC solution started to be used, the final product was actually more expensive due to lower yield. The developments in integrated technology through the years allowed the integration of more components in lesser area with a better yield. Thus, SoCs became a widely used solution to reduced the cost of the final product, integrating into a single-chip the main parts of a system: analog, digital and memory. As integrated technology kept scaling down to allow a higher density of transistors and thus providing more functionality with the same die area, the analog RF parts of the SoC became a bottleneck to cost reduction as inductors occupy a large die area and do not scale down with technology. Hence, the trend moves toward the research and design of inductor-less SoCs that further reduce the cost of the final solution. Also, as the demand for home networking high-data-rates communication systems has increased over the last decade, several standards have been developed to satisfy the requirements of each application, the most popular being wireless local area networks (WLANs) based on the IEEE 802.11 standard. However, poor signal propagation across walls make WLANs unsuitable for high-speed applications such as high-definition in-home video streaming, leading to the development of wired technologies using the existing in-home infrastructure. The ITU-T G.hn recommendation (G.9960 and G.9961) unifies the most widely used wired infrastructures at home (coaxial cables, phone lines and power lines) into a single standard for high-speed data transmission of up to 1 Gb/s. The G.hn recommendation defines a unified networking over power lines, phone lines and coaxial cables with different plans for baseband and RF. The RF-coax bandplan, where this thesis is focused, uses 50 MHz and 100 MHz bandwidth channels with 256 and 512 carriers respectively. The center frequency can range from 350 MHz to 2450 MHz. The recommendation specifies a transmission power limit of 5 dBm for the 50 MHz bandplan and 8~dBm for the 100 MHz bandplan, therefore the maximum transmitted power in each carrier is the same for both bandplans. Due to the nature of an in-home wired environment, receivers that can handle both very large and very small amplitude signals are required; when transmitter and receiver are connected on the same electric outlet there is no channel attenuation and the signal-to-noise-plus-distortion ratio (SNDR) is dominated by the receiver linearity, whereas when transmitter and receiver are several rooms apart channel attenuation is high and the SNDR is dominated by the receiver noise figure. The high dynamic range specifications for these receivers require the use of configurable-gain topologies that can provide both high-linearity and low-noise for different configurations. Thus, this thesis has been aimed at researching high dynamic range broadband inductor-less topologies to be used as the RF front-end for a G.hn receiver complying with the provided specifications. A large part of the thesis has been focused on the design of the input amplifier of the front-end, which is the most critical stage as the noise figure and linearity of the input amplifier define the achievable overall specifications of the whole front-end. Three prototypes has been manufactured using a 65 nm CMOS process: two input RFPGAs and one front-end using the second RFPGA prototype.El "sistema en un chip" (SoC) fue adoptado recientemente como una de las soluciones para reducir el coste de sistemas integrados. Cuando se empezó a utilizar la solución SoC, el producto final era más caro debido al bajo rendimiento de producción. Los avances en tecnología integrada a lo largo de los años han permitido la integración de más componentes en menos área con mejoras en rendimiento. Por lo tanto, SoCs pasó a ser una solución ampliamente utilizada para reducir el coste del producto final, integrando en un único chip las principales partes de un sistema: analógica, digital y memoria. A medida que las tecnologías integradas se reducían en tamaño para permitir una mayor densisdad de transistores y proveer mayor funcionalidad con la misma área, las partes RF analógicas del SoC pasaron a ser la limitación en la reducción de costes ya que los inductores ocupan mucha área y no escalan con la tecnología. Por lo tanto, las tendencias en investigación se mueven hacia el diseño de SoCs sin inductores que todavía reducen más el coste final del producto. También, a medida que la demanda en sistemas de comunicación domésticos de alta velocidad ha crecido a lo largo de la última década, se han desarrollado varios estándares para satisfacer los requisitos de cada aplicación, siendo las redes sin hilos (WLANs) basadas en el estándar IEEE 802.11 las más populares. Sin embargo, una pobre propagación de señal a través de las paredes hacen que las WLANs sean inadecuadas para aplicaciones de alta-velocidad como transmisión de vídeo de alta definición en tiempo real, resultando en el desarrollo de tecnologías con hilos utilizando la infraestructura existente en los domicilios. La recomendación ITU-T G.hn (G.9960 and G.9961) unifica las principales infraestructuras con hilos domésticas (cables coaxiales, línias de teléfono y línias de electricidad) en un sólo estándar para la transmisión de datos hasta 1 Gb/s. La recomendación G.hn define una red unificada sobre línias de electricidad, de teléfono y coaxiales con diferentes esquemas para banda base y RF. El esquema RF-coax en el cual se basa esta tesis, usa canales con un ancho de banda de 50 MHz y 100 MHz con 256 y 512 portadoras respectivamente. La frecuencia centra puede variar desde 350 MHz hasta 2450 MHz. La recomendación especifica un límite en la potencia de transmisión de 5 dBm para el esquema de 50 MHz y 8 dBm para el esquema de 100 MHz, de tal forma que la potencia máxima por portadora es la misma en ambos esquemas. Debido a la estructura de un entorno doméstico con hilos, los receptores deben ser capaces de procesar señales con amplitud muy grande o muy pequeña; cuando transmisor y receptor están conectados en la misma toma eléctrica no hay atenuación de canal y el ratio de señal a rudio más distorsión (SNDR) está dominado por la linealidad del receptor, mientras que cuando transmisor y receptor están separados por varias habitaciones la atenuación es elevada y el SNDR está dominado por la figura de ruido del receptor. Los elevados requisitos de rango dinámico para este tipo de receptores requieren el uso de topologías de ganancia configurable que pueden proporcionar tanto alta linealidad como bajo ruido para diferentes configuraciones. Por lo tanto, esta tesis está encarada a la investigación de topologías sin inductores de banda ancha y elevado rango dinámico para ser usadas a la entrada de un receptor G.hn cumpliendo con las especificaciones proporcionadas. Una gran parte de la tesis se ha centrado en el diseño del amplificador de entrada al ser la etapa más crítica, ya que la figura de ruido y linealidad del amplificador de entrada definen lás máximas especificaciones que el sistema puede conseguir. Se han fabricado 3 prototipos con un proceso CMOS de 65 nm: 2 amplificadores y un sistema completo con amplificador y mezclador.Postprint (published version

Développement d'une architecture innovante de récepteur radar à 77 GHz et démonstration en CMOS 28 nm FDSOI

Grâce à sa capacité à détecter des cibles éloignées malgré une mauvaise visibilité, le radar automobile à 77 GHz joue un rôle important dans l'aide à la conduite. L'utilisation des fréquences millimétriques offre une bonne résolution et une importante capacité d'intégration des circuits. C'est aussi un défi car il faut satisfaire un cahier des charges exigeant sur le bruit et la linéarité du récepteur. Les technologies SiGe BiCMOS ont été les premières utilisées pour la conception de récepteurs radar à 77 GHz. De bons résultats ont été obtenus en se basant sur des architectures utilisant des mélangeurs actifs. Cependant l'utilisation des technologie BiCMOS se traduisait par une consommation élevée, une faible capacité d'intégration et des coûts de production importants. Récemment, l'intégration des procédés CMOS menant à l'augmentation des fréquences de transition rend ces technologies plus attractives pour les applications nécessitant un faible coût et la cointégration de plusieurs fonctions au sein d'une même puce. La littérature sur les récepteurs radars en technologie CMOS à 77 GHz montre que les architectures inspirées par les technologies BiCMOS ne sont pas pertinentes pour cette application. Le but de cette thèse et de montrer que l'utilisation de techniques propres aux technologie CMOS comme l'échantillonnage et l'utilisation de portes logiques permet d'obtenir de très bonnes performances. Dans ce travail, deux nouvelles architectures de récepteurs radars basées sur le principe d'échantillonnage sont proposées. La première architecture est basée sur un mélangeur passif échantillonné qui permet d'obtenir un très bon compromis bruit/linéarité. La seconde exploite les propriétés des mélangeurs sous-échantillonnés afin utiliser une fréquence d'OL trois fois inférieure à la fréquence RF offrant ainsi de très intéressantes simplifications au niveau de la chaîne de distribution du signal d'OL du récepteur. Le contexte de cette étude est expliqué dans le 1er chapitre qui présente les exigences de conception liées à l'application radar et fourni une analyse de l'état de l'art des récepteurs à 77 GHZ. Le chapitre suivant décrit le principe de fonctionnement et l'implémentation d'un mélangeur échantillonné à 77 GHz en technologie CMOS 28- nm FDSOI. Une topologie de mélangeur sous-échantillonné utilisant une fréquence d'OL de 26 GHz pour convertir des signaux RF autour de 77 GHz est ensuite détaillée dans le chapitre 3. Le chapitre 4 conclut cette étude en détaillant l'intégration des mélangeurs étudiés dans les chapitres précédents avec un amplificateur faible bruit dans différents récepteurs radars. Ces architectures de récepteurs basées sur l'échantillonnage sont ensuite comparées entre elles et avec l'état de l'art montrant ainsi leurs avantages et inconvénients. Les résultats de cette comparaison confirment l'intérêt des techniques d'échantillonnage pour la conversion de fréquence dans le cadre de l'application radar.With its ability to detect distant targets under harsh visibility conditions, the 77 GHz automotive radar plays a key role in driving safety. Using mm-wave frequencies allow a good range resolution, a better circuit integration and a wide modulation bandwidth. This is also a challenge for circuit designers who must fulfill stringent requirements especially on the receiver front-end. First 77 GHz radar receivers were manufactured with SiGe BiCMOS processes benefiting from the high transition frequency and high breakdown voltage of Hetero-junction Bipolar Transistors (HBT). Good results have been achieved with active-mixer-based architectures, but these technologies suffer from high power consumptions, limited integration capacity and large production cost. More recently, the scaling down of CMOS processes (coming together with the increase of the transition frequency of the transistors) makes CMOS a good candidate for 77 GHz circuit design, especially when cost target requires single chip solutions. The literature related to CMOS radar receivers highlights that receivers based on BiCMOS architectures generally show poor performances. The aim of this work is to demonstrate that using CMOS specific technics such as sampling and the use of high-speed digital gates should enhance the performance of the receivers. In this work, two innovative radar receiver architectures based on the sampling principle are proposed. The first one shows that this principle can be extended to millimeter wave frequencies to benefit from a very good noise/linearity trade-off. While the second one uses this principle to converts a 77 GHz RF signal by using a 26 GHz LO frequency thus simplifying the LO distribution chain of the receiver. The background of this study is introduced in the chapter 1 presenting the design trade-off related to the 77 GHz radar receiver and provides a review of the existing solutions. The following chapter describes the sampling mixer principle and the implementation of a 77 GHz sampling mixer in 28-nm FDSOI CMOS technology. Then, a sub- sampling mixer topology allowing to convert an RF signal around 77 GHz using a 26 GHz LO frequency is detailed in the chapter 3. The chapter 4 draws the conclusion of this study by showing the implementation of the two proposed sampling-based mixers with a low noise amplifier in 77 GHz front ends. These receiver architectures are compared with the state of the art highlighting the strengths and weaknesses of the proposed solutions. The results of this study demonstrates that using sampling for down conversion can be convenient to address millimeter-wave frequency applications