A -5 dBm 400MHz OOK Transmitter for Wireless Medical Application

A 400 MHz high efficiency transmitter forwireless medical application is presented in this paper. Transmitter architecture with high-energy efficiencies isproposed to achieve high data rate with low powerconsumption. In the on-off keying transmitters, the oscillatorand power amplifier are turned off when the transmittersends 0 data. The proposed class-e power amplifier has highefficiency for low level output power. The proposed on-offkeying transmitter consumes 1.52 mw at -5 dBm output by 40Mbps data rate and energy consumption 38 pJ/bit. Theproposed transmitter has been designed in 0.18µm CMOStechnology

A 2.4 GHz CMOS class-F power amplifier with reconfigurable load-impedance matching

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.A novel reconfigurable CMOS class-F power amplifier (PA) at 2.4 GHz is proposed in this paper. It is able to match the output load variations mainly due to the effect of hand and head on a mobile phone. The effect of load variation on power-added efficiency (PAE), output power, and distortion is compensated by reconfiguring the output network using an impedance tuner. The tuner controls the output matching at fundamental frequency without affecting the class-F harmonic tuning up to 3rd harmonic. To the best of our knowledge, this is the first design of a CMOS class-F PA addressed to compensate the effect of load variation. Measurement results for 50 ohm load impedance show a maximum PAE of 26% and maximum output power of 19.2 dBm. The measured total harmonic distortion is 4.9%. Measurement results for load values other than 50 ohm show that PAE increases from 6.5% (not-tuned PA) up to 19.9% (tuned PA) with the same output power (19.2 dBm). Tuning also reduces the adjacent-channel leakage ratio by 5 dB and the spectral regrowth of a Wi-Fi signal at the PA output. The size of the fabricated chip is 1.6 mm × 1.6 mm.Peer ReviewedPostprint (author's final draft

Design of a class-F power amplifier with reconfigurable output harmonic termination in 0.13 µm CMOS

Next generation wireless communication technology requires mobile devices and base stations to support multiband multimode frequencies with higher data rate because of the type of enriched and enhanced features and services that are provided to the end user. The challenge for next generation PA designers is to provide high efficiency, output power and good linearity across multiple frequency bands, modulation standards and bandwidth. Current industry solution involves parallel PAs dedicated to a single band of operation. As more and more features are added, more and more PAs will be required with increasing cost, area and complexity. As a solution to this problem, one tunable fully integrated class-F power amplifier with reconfigurable output harmonic termination is proposed, designed, fabricated and tested with a commercially available 0.13µm CMOS process technology. By using the coupling between the primary and the secondary winding of an on chip transformer with a variable secondary termination capacitance, the second and third harmonic short and open circuit frequencies are dynamically tuned from 700 MHz to 1200 MHz and achieve high efficiency and output power. To overcome CMOS process low break down voltage, a series voltage combining approach is used for the power device to boost output power, by allowing the power supply to exceed process limits. The fabricated die was packaged and mounted to a printed circuit board for evaluation. Compared to previously publish fully integrated PAs, our design exhibits superior peak power added efficiency, 48.4%, and decent saturated output power and power gain of 24.6 dBm and 16.5 dB respectively with reconfigurability from 700 MHz to 1200 MHz

A Review of Highly Efficient Class F Power Amplifier Design Technique in Gigahertz Frequencies

Highly efficient class F power amplifier (PA) in Gigahertz (GHz) frequencies for wireless application is reviewed in this paper. The study focused on the technique used in designing a class F PA especially at GHz frequencies. Several works on the class F PA with different semiconductor technologies from year 2001 to 2016 are discussed. Recent works on class F PA in wireless applications are examined and a comparison of the PA performances of various techniques is presented. Key performance indicators for high efficiency class F PA include power added efficiency (PAE) and output power (Pout)

RF to Millimeter-wave Linear Power Amplifiers in Nanoscale CMOS SOI Technology

The low manufacturing cost, integration capability with baseband and digital circuits, and high operating frequency of nanoscale CMOS technologies have propelled their applications into RF and microwave systems. Implementing fully-integrated RF to millimeter-wave (mm-wave) CMOS power amplifiers (PAs), nevertheless, remains challenging due to the low breakdown voltages of CMOS transistors and the loss from on-chip matching networks. These limitations have reduced the design space of CMOS power amplifiers to narrow-band, low linearity metrics often with insufficient gain, output power, and efficiency. A new topology for implementing power amplifiers based on stacking of CMOS SOI transistors is proposed. The input RF power is coupled to the transistors using on-chip transformers, while the gate terminal of teach transistor is dynamically biased from the output node. The output voltages of the stacked transistors are added constructively to increase the total output voltage swing and output power. Moreover, the stack configuration increases the optimum load impedance of the PA to values close to 50 ohm, leading to power, efficiency and bandwidth enhancements. Practical design issues such as limitation in the number of stacked transistors, gate oxide breakdown, stability, effect of parasitic capacitances on the performance of the PA and large chip areas have also been addressed. Fully-integrated RF to mm-wave frequency CMOS SOI PAs are successfully implemented and measured using the proposed topology

Development of a High-Efficiency, Low-Power RF Power Amplifier for Use in a High-Temperature Environment

This thesis presents a study of the design of a high efficiency, low power, RF power amplifier that can operate over an extended temperature range. The amplifier has been implemented as a hybrid circuit with the active device fabricated in a 0.5μm silicon-on- sapphire CMOS technology and passive components implemented off-chip. First a review of power amplifiers is given. Next design considerations for low power, high efficiency amplifiers are presented. Finally design details and measurement results from a low-power Class E amplifier are presented. When operated with an output power of 1 mW, the Class E amplifier achieves an efficiency greater than 40% over the frequency band 250 MHz to 310 MHz at 25 C and from 265 MHz to 295 MHz at 200 C

Compact Power Amplifiers Using Circuit Level and Spatial Power Combining Techniques.

High power, high efficiency, and compact size are important performance measures of power amplifiers used in transmitters for civilian, as well military communications and radars. It is difficult to achieve all the above performance measures at the same time. Several new high power, high efficiency, and compact size power amplifier designs are introduced in this dissertation. A new circuit-level power combining technique, which is capable of achieving high power levels while maintaining high efficiency and small size, is introduced. It consists of cascoded class-E power amplifiers based on a high voltage / high power (HiVP) design technique. Several power amplifiers are designed and implemented using microstrip circuits and packaged laterally diffused metal oxide semiconductor (LDMOS) devices at VHF. An output power of 71 W with 31.5 dB of gain and power added efficiency (PAE) of 69 % is achieved using this technique. Design equations for HiVP class-E power amplifier are also derived. To the best of the author’s knowledge, this is the first demonstration of a class-E HiVP power amplifier. Subsequently, a compact millimeter wave spatial power combining technique using serially fed antenna arrays is introduced in this dissertation. Several power amplifiers are incorporated with antennas in a serially fed array in order to combine their output power in free space. Design techniques for broadband serially fed antenna arrays employing new lossless negative group delay (NGD) circuits are reported. Several lossless NGD circuits are designed at Ka-band, X-band, and S-band frequencies. NGD is generated by employing the resonance behavior of microstrip-fed quasi-Yagi antennas, microstrip patch antennas and amplifiers with matching circuits.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/107248/1/walomar_1.pd

Efficient, High power Precision RF and mmWave Digital Transmitter Architectures

Digital transmitters offer several advantages over conventional analog transmitters such as reconfigurability, elimination of scaling-unfriendly, power hungry and bulky analog blocks and portability across technology. The rapid advancement of technology in CMOS processes also enables integration of complex digital signal processing circuitry on the same die as the digital transmitter to compensate for their non-idealities. The use of this digital assistance can, for instance, enable the use of highly efficient but nonlinear switching-class power amplifiers by compensating for their severe nonlinearity through digital predistortion. While this shift to digitally intensive transmitter architectures is propelled by the benefits stated above, several pressing challenges arise that vary in their nature depending on the frequency of operation - from RF to mmWave. Millimeter wave CMOS power amplifiers have traditionally been limited in output power due to the low breakdown voltage of scaled CMOS technologies and poor quality of on-chip passives. Moreover, high data-rates and efficient spectrum utilization demand highly linear power amplifiers with high efficiency under back-off. However, linearity and high efficiency are traditionally at odds with each other in conventional power amplifier design. In this dissertation, digital assistance is used to relax this trade-off and enable the use of state-of-the-art switching class power amplifiers. A novel digital transmitter architecture which simultaneously employs aggressive device-stacking and large-scale power combining for watt-class output power, dynamic load modulation for linearization, and improved efficiency under back-off by supply-switching and load modulation is presented. At RF frequencies, while the problem of watt-class power amplification has been long solved, more pressing challenges arise from the crowded spectrum in this regime. A major drawback of digital transmitters is the absence of a reconstruction filter after digital-to-analog conversion which causes the baseband quantization noise to get upconverted to RF and amplified at the output of the transmitter. In high power transmitters, this upconverted noise can be so strong as to prevent their use in FDD systems due to receiver desensitization or impose stringent coexistence challenges. In this dissertation, new quantization noise suppression techniques are presented which, for the first time, contribute toward making watt-class fully-integrated digital RF transmitters a viable alternative for FDD and coexistence scenarios. Specifically, the techniques involve embedding a mixed-domain multi-tap FIR filter within highly-efficient watt-class switching power amplifiers to suppress quantization noise, enhancing the bandwidth of noise suppression, enabling tunable location of suppression and overcoming the limitations of purely digital-domain filtering techniques for quantization noise

고효율 고전압 포락선 추적 전력 증폭기에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 공과대학 전기·컴퓨터공학부, 2017. 8. 서광석.In this dissertation, two advanced techniques to solve system issues in envelope tracking power amplifier (ET PA) is presented. First of all, a two-stage broadband CMOS stacked FET RF power amplifier (PA) with a reconfigurable interstage matching network is developed for wideband envelope tracking (ET). The proposed RF PA is designed based on Class-J mode of operation, where the output matching is realizedwith a two-section low-pass matching network. To overcome the bandwidth (BW) limitation from the high- interstage impedance, a reconfigurable matching network is proposed, allowing a triple frequency mode of operation using two RF switches. The proposed RF PA is fabricated in a 0.32-μm silicon-on-insulator CMOS process and shows continuous wave (CW) power-added efficiencies (PAEs) higher than 60% from 0.65 to 1.03 GHz with a peak PAE of 69.2% at 0.85 GHz. The complete ET PA system performance is demonstrated using the envelope amplifier fabricated on the same process. When measured using a 20-MHz BW long-term evolution signal, the overall system PAE of the ET PA is higher than 40% from 0.65 to 0.97 GHz while evolved universal terrestrial radio access (E-UTRA) adjacent channel leakage ratios (ACLRs) are better than –33 dBc across the entire BW after memoryless digital pre-distortion. To our knowledge, this study represents the highest overall system performance in terms of PAE and BW among the published broadband ET PAs, including GaAs HBT and SiGe BiCMOS. Second, a high-efficiency gallium-nitride (GaN) envelope amplifier (EA) is developed using class-E2 architecture for wideband LTE applications. The proposed EA consists of a class-E2 resonant converter which output voltage is controlled by a frequency modulator. With a pulse frequency modulation (PFM) signal, the output of the converter can achieve a linear response to the input wideband envelope signal. The frequency modulator with a cross-coupled oscillator and a driver using stacked-FETs structure is fabricated using 0.28-μm SOI CMOS process. The class-E2 converter and PA have been implemented using a commercial GaN device. The envelope amplifier (EA) achieves 74.7% efficiency into a 50 Ω load for a 20-MHz BW LTE signal with a 7.5 dB peak-to-average power ratio (PAPR) and there is no efficiency degradation as the LTE signal bandwidth increases to 160-MHz. The ET transmitter system demonstrated using the CMOS and GaN shows an overall system efficiency of 47.4% at 35.4 dBm with 20-MHz BW LTE signal centered at 3.5 GHz. The measured E-UTRA ACLR of ET PA is –33.8 dBc at 34.4 dBm output power before linearization and –42.9 dBc at the same output power after memory digital pre-destination (DPD). When tested using 80-MHz BW LTE signal, the overall system PAE reaches 46.5% at 35.3 dBm output power and E-UTRA ACLR was measured by –31.5 dBc at 34.4 dBm output power. A wideband performance is characterized using various bandwidth LTE signals which shows only 2.3 dB ACLR degradation without PAE degradation as the signal bandwidth is increased from 20- to 80-MHz. The proposed method is a first demonstration of GaN EA cover 160-MHz BW LTE signals and overcomes the efficiency degradation of the conventional EA as the signal bandwidth increase.Abstract Contents List of Tables List of Figures 1. Introduction 1.1 Motivation 1.2 Dissertation organization 2. Broadband CMOS Stacked RF Power Amplifier Using Reconfigurable Interstage Network for Wideband Envelope Tracking 2.1 Introduction 2.2 Two-stage broadband class-J PA 2.2.1 Review of the class-J PA 2.2.2 BW limitation in multi-stage PAs and proposed solution 2.2.3 Output matching netwok 2.2.4 Reconfigurable interstage matching network 2.3 Design and implementation of ET PA 2.3.1 Power amplifier design 2.3.2 Envelope amplifier design 2.4 Measurement results 2.5 Conclusions 2.6 References 3. A GaN Envelope Amplifier using Class-E2 Architecture for Wideband Envelope Tracking Applications 3.1 Introduction 3.2 Operation principle of the proposed envelope amplifier 3.2.1 Operation principle of class-E inverter and rectifier 3.2.2 Operation comparison of class-E2 between PWM and PFM 3.3 Detailed ET PA design and simulation 3.3.1 Envelope amplifier design using current-starved VCO (CSVCO) 3.3.2 Envelope amplifier design using cross-coupled VCO (CCVCO) 3.4 Measurement results 3.5 Conclusions 3.6 References 4. Conclusions and Future Works Abstract in KoreanDocto

Design of an RF CMOS Power Amplifier for Wireless Sensor Networks

The Power Amplifier (PA) is the last Radio Frequency (RF) building block in a transmitter, directly driving an antenna. The low power RF input signal of the PA is amplified to a significant power RF output signal by converting DC power into RF power. Since the PA consumes a majority of the power, efficiency plays one of the most important roles in a PA design. Designing an efficient, fully integrated RF PA that can operate at low supply voltage (1.2V), low power, and low RF frequency (433MHz) is a major challenge. The class E Power Amplifier, which is one type of switch mode PA, is preferred in such a scenario because of its higher theoretical efficiency compared to linear power amplifiers. A controllable class E RF power amplifier design implemented in 0.13 µm CMOS process is presented. The circuit was designed, simulated, laid out, fabricated, and tested. The PA will be integrated as a part of a complete wireless transceiver system using the same process