Design of a class-F power amplifier with reconfigurable output harmonic termination in 0.13 µm CMOS

Abstract

Next generation wireless communication technology requires mobile devices and base stations to support multiband multimode frequencies with higher data rate because of the type of enriched and enhanced features and services that are provided to the end user. The challenge for next generation PA designers is to provide high efficiency, output power and good linearity across multiple frequency bands, modulation standards and bandwidth. Current industry solution involves parallel PAs dedicated to a single band of operation. As more and more features are added, more and more PAs will be required with increasing cost, area and complexity. As a solution to this problem, one tunable fully integrated class-F power amplifier with reconfigurable output harmonic termination is proposed, designed, fabricated and tested with a commercially available 0.13µm CMOS process technology. By using the coupling between the primary and the secondary winding of an on chip transformer with a variable secondary termination capacitance, the second and third harmonic short and open circuit frequencies are dynamically tuned from 700 MHz to 1200 MHz and achieve high efficiency and output power. To overcome CMOS process low break down voltage, a series voltage combining approach is used for the power device to boost output power, by allowing the power supply to exceed process limits. The fabricated die was packaged and mounted to a printed circuit board for evaluation. Compared to previously publish fully integrated PAs, our design exhibits superior peak power added efficiency, 48.4%, and decent saturated output power and power gain of 24.6 dBm and 16.5 dB respectively with reconfigurability from 700 MHz to 1200 MHz

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