Active Inductor with Feedback Resistor Based Voltage Controlled Oscillator Design for Wireless Applications

This paper presents active inductor based VCO design for wireless applications based on analysis of active inductor models (Weng-Kuo Cascode active inductor & Liang Regular Cascode active inductor) with feedback resistor technique. Embedment of feedback resistor results in the increment of inductance as well as the quality factor whereas the values are [email protected] (Liang) and [email protected] (Weng- Kuo). The Weng-Kuo active inductor based VCO shows a tuning frequency of 1.765GHz ~2.430GHz (31.7%), while consuming a power of 2.60 mW and phase noise of -84.15 dBc/Hz@1MHz offset. On the other hand, Liang active inductor based VCO shows a frequency range of 1.897GHz ~2.522GHz (28.28%), while consuming a power of 1.40 mW and phase noise of -80.79 dBc/Hz@1MHz offset. Comparing Figure-of-Merit (FoM), power consumption, output power and stability in performance, designed active inductor based VCOs outperform with the state-of-the-art

A low power wideband varactorless VCO using tunable active inductor

This paper presents a wideband varactorless voltage controlled oscillator (VCO) based on tunable active inductor in 90 nm CMOS process which yields a tuning range of 1.22 GHz to 3.7 GHz having a tuning scope of 100.5%. The designed VCO can be used for wideband wireless applications. The proposed VCO consumes a very low power (1.05 ~ 2.5) mW with the change of tuning voltages (0.3 ~ 0.9) V and provides a differential output power of (1.17 ~ -5.13) dBm. The VCO exhibits phase noise of -80.50 dBc/[email protected] GHz and the Figure of Merit (FOM) is -147.73 dBc/Hz @2.74 GHz at 1MHz offset frequency. Achievement of high tuning range by altering the inductance of inductor which paves the way for eliminating the MOS varactor that recedes the overall silicon area consumption, is the noteworthy outcome of the proposed VCO. Furthermore, considering the dc power consumption, figure of merit (FOM) and consistency of performance parameters over tuning range, the proposed VCO outstrips the other referred VCOs

Concepts and methods in optimization of integrated LC VCOs

Underlying physical mechanisms controlling the noise properties of oscillators are studied. This treatment shows the importance of inductance selection for oscillator noise optimization. A design strategy centered around an inductance selection scheme is executed using a practical graphical optimization method to optimize phase noise subject to design constraints such as power dissipation, tank amplitude, tuning range, startup condition, and diameters of spiral inductors. The optimization technique is demonstrated through a design example, leading to a 2.4-GHz fully integrated, LC voltage-controlled oscillator (VCO) implemented using 0.35-μm MOS transistors. The measured phase-noise values are -121, -117, and -115 dBc/Hz at 600-kHz offset from 1.91, 2.03, and 2.60-GHz carriers, respectively. The VCO dissipates 4 mA from a 2.5-V supply voltage. The inversion mode MOSCAP tuning is used to achieve 26% of tuning range. Two figures of merit for performance comparison of various oscillators are introduced and used to compare this work to previously reported results

USING VCOS AS RF MEASURING DEVICES

This thesis presents an alternative way to test the amount of energy harvested by an antenna. Accurately measuring the amount of energy an antenna harvests is a challenge. The test equipment that touches the antenna can greatly affect the results of the test. Using a VCO to measure an antenna's harvested power enables accuracy and prevents the need to attach testing equipment. The VCO is powered by a harvesting antenna. The frequency produced is then output to a transmitting antenna. The output frequency of the VCO can easily be determined and then used to look up the power from the characteristics of the VCO. A background study of types of VCOs, and VCOs available on the market will also be included in this thesis. Finally the experiment setups and results will be presented

A dual-mode Q-enhanced RF front-end filter for 5 GHz WLAN and UWB with NB interference rejection

The 5 GHz Wireless LAN (802.11a) is a popular standard for wireless indoor communications providing moderate range and speed. Combined with the emerging ultra Wideband standard (UWB) for short range and high speed communications, the two standards promise to fulfil all areas of wireless application needs. However, due to the overlapping of the two spectrums, the stronger 802.11a signals tend to interfere causing degradation to the UWB receiver. This presents one of the main technical challenges preventing the wide acceptance of UWB. The research work presented in this thesis is to propose a low cost RF receiver front-end filter topology that would resolve the narrowband (NB) interference to UWB receiver while being operable in both 802.11a mode and UWB mode. The goal of the dual mode filter design is to reduce cost and complexity by developing a fully integrated front-end filter. The filter design utilizes high Q passive devices and Q-enhancement technique to provide front-end channel-selection in NB mode and NB interference rejection in UWB mode. In the 802.11a NB mode, the filter has a tunable gain of 4 dB to 25 dB, NF of 8 dB and an IIP3 between -47 dBm and -18 dBm. The input impedance is matched at -16 dB. The frequency of operation can be tuned from 5.15 GHz to 5.35 GHz. In the UWB mode, the filter has a gain of 0 dB to 8 dB across 3.1 GHz to 9 GHz. The filter can reject the NB interference between 5.15 GHz to 5.35 GHz at up to 60 dB. The Q of the filter is tunable up to a 250 while consuming a maximum of 23.4 mW of power. The fully integrated dual mode filter occupies a die area of 1.1 mm2

Circuit design and technological limitations of silicon RFICs for wireless applications

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 201-206).Semiconductor technologies have been a key to the growth in wireless communication over the past decade, bringing added convenience and accessibility through advantages in cost, size, and power dissipation. A better understanding of how an IC technology affects critical RF signal chain components will greatly aid the design of wireless systems and the development of process technologies for the increasingly complex applications that lie on the horizon. Many of the evolving applications will embody the concept of adaptive performance to extract the maximum capability from the RF link in terms of bandwidth, dynamic range, and power consumption-further engaging the interplay of circuits and devices is this design space and making it even more difficult to discern a clear guide upon which to base technology decisions. Rooted in these observations, this research focuses on two key themes: 1) devising methods of implementing RF circuits which allow the performance to be dynamically tuned to match real-time conditions in a power-efficient manner, and 2) refining approaches for thinking about the optimization of RF circuits at the device level. Working toward a 5.8 GHz receiver consistent with 1 GBit/s operation, signal path topologies and adjustable biasing circuits are developed for low-noise amplifiers (LNAs) and voltage-controlled oscillators (VCOs) to provide a facility by which power can be conserved when the demand for sensitivity is low. As an integral component in this effort, tools for exploring device level issues are illustrated with both circuit types, helping to identify physical limitations and design techniques through which they can be mitigated.(cont.) The design of two LNAs and four VCOs is described, each realized to provide a fully-integrated solution in a 0.5 tm SiGe BiCMOS process, and each incorporating all biasing and impedance matching on chip. Measured results for these 5-6GHz circuits allow a number of poignant technology issues to be enlightened, including an exhibition of the importance of terminal resistances and capacitances, a demonstration of where the transistor fT is relevant and where it is not, and the most direct comparison of bipolar and CMOS solutions offered to date in this frequency range. In addition to covering a number of new circuit techniques, this work concludes with some new views regarding IC technologies for RF applications.by Donald A. Hitko.Ph.D

Design and implementation of a frequency synthesizer for an IEEE 802.15.4/Zigbee transceiver

The frequency synthesizer, which performs the main role of carrier generation for the down-conversion/up-conversion operations, is a key building block in radio transceiver front-ends. The design of a synthesizer for a 2.4 GHz IEEE 802.15.4/Zigbee transceiver forms the core of this work. This thesis provides a step-by-step procedure for the design of a frequency synthesizer in a transceiver environment, from the mapping of standard-specifications to its integrated circuit implementation in a CMOS technology. The results show that careful system level planning leads to high-performance realizations of the synthesizer. A strategy of using different supply voltages to enhance the performance of each building block is discussed. A section is presented on layout and board level issues, especially for radio-frequency systems, and their effect on synthesizer performance. The synthesizer consumes 15.5 mW and meets the specifications of the 2.4 GHz IEEE 802.15.4/Zigbee standard. It is capable of 5 GHz operation with a VCO sensitivity of 135 MHz/V and a tuning range of 700 MHz. It can be seen that the adopted methodology can be used for the design of high-performance frequency synthesizers for any narrow-band wireless standard