11 research outputs found
LOW POWER ANALOG-TO-DIGITAL CONVERSION CIRCUIT FOR AUDIO APPLICATION
In recent years, demand for a mixed signal LSI used for electronic equipment is increasing. High precision and low power consumption are required for ADCs for audio applications. ΔΣ ADC is a method to realize highly accurate AD conversion. However, power efficiency is poor as compared with general ADC configuration. This paper proposes a two steps ADC using a SAR-ADC and ΔΣ-ADC. The SAR-ADC arranged in the preceding stage can relax the required performance of the analog circuit of ΔΣ ADC. Therefore, low power consumption can be achieved. This proposal is designed with 0.18um CMOS. The performance of proposed system is confirmed by system simulation using MATLAB / Simulink and circuit simulation using Virtuoso / spectre, respectively
700mV low power low noise implantable neural recording system design
This dissertation presents the work for design and implementation of a low power, low noise neural recording system consisting of Bandpass Amplifier and Pipelined Analog to Digital Converter (ADC) for recording neural signal activities. A low power, low noise two stage neural amplifier for use in an intelligent Radio-Frequency Identification (RFID) based on folded cascode Operational Transconductance Amplifier (OTA) is utilized to amplify the neural signals. The optimization of the number of amplifier stages is discussed to achieve the minimum power and area consumption. The amplifier power supply is 0.7V. The midband gain of amplifier is 58.4dB with a 3dB bandwidth from 0.71 to 8.26 kHz. Measured input-referred noise and total power consumption are 20.7 μVrms and 1.90 μW respectively. The measured result shows that the optimizing the number of stages can achieve lower power consumption and demonstrates the neural amplifier's suitability for instu neutral activity recording. The advantage of power consumption of Pipelined ADC over Successive Approximation Register (SAR) ADC and Delta-Sigma ADC is discussed. An 8 bit fully differential (FD) Pipeline ADC for use in a smart RFID is presented in this dissertation. The Multiplying Digital to Analog Converter (MDAC) utilizes a novel offset cancellation technique robust to device leakage to reduce the input drift voltage. Simulation results of static and dynamic performance show this low power Pipeline ADC is suitable for multi-channel neural recording applications. The performance of all proposed building blocks is verified through test chips fabricated in IBM 180nm CMOS process. Both bench-top and real animal test results demonstrate the system's capability of recording neural signals for neural spike detection
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Low-power double-sampled delta-sigma modulator for broadband applications
High speed and high resolution analog-to-digital converter is a key building block for broadband wireless communications, high definition video applications, medical images and so on. By leveraging the down scaling of the latest CMOS technology and the noise shaping properties, delta-sigma (ΔΣ) ADCs are able to achieve wide-band operation and high accuracy simultaneously. At first in this thesis, two novel techniques which can be applied to high performance ΔΣ ADC design are proposed. The first one is a modulator architectural innovation that is able to effectively solve the feedback timing constraints in a double-sampled ΔΣ modulator. The second one is a transistor level improvement to reduce the hardware consumption in a standard Date Weighted Averaging (DWA) realization.
Next, charge-pump (CP) based switched-capacitor (SC) integrator is discussed. A cross-coupling technique is proposed to eliminate parasitic capacitor effect in a CP based SC integrator. Also design methodologies are introduced to incorporate a modified CP based SC integrator into a low-distortion ΔΣ modulator. A second-order ΔΣ modulator was designed and simulated to verify the proposed modulator topology.
Finally, design of a double-sampled broadband 12-bit ΔΣ modulator is presented. To achieve very low power consumption, this modulator utilizes the following two key design techniques:
1. Double sampled integrator to increase the effective over-sampling ratio.
2. Capacitor reset technique allows the use of only one feedback DAC at the front end of the modulator to completely eliminate the quantization noise folding back.
A 2+2 cascaded topology with 3-bit internal quantizer is used in this ΔΣ modulator to adequately suppress the quantization noise while guarantee the loop stability. This ΔΣ modulator was fabricated in a 90nm digital CMOS process and achieves an SNDR of 70dB within a 5MHz signal bandwidth. The modulator occupies a silicon area of 0.5mm² and consumes 10mW with a supply voltage of 1.2V
Low-Power Low-Noise CMOS Analog and Mixed-Signal Design towards Epileptic Seizure Detection
About 50 million people worldwide suffer from epilepsy and one third of them have seizures that are refractory to medication. In the past few decades, deep brain stimulation (DBS) has been explored by researchers and physicians as a promising way to control and treat epileptic seizures. To make the DBS therapy more efficient and effective, the feedback loop for titrating therapy is required. It means the implantable DBS devices should be smart enough to sense the brain signals and then adjust the stimulation parameters adaptively.
This research proposes a signal-sensing channel configurable to various neural applications, which is a vital part for a future closed-loop epileptic seizure stimulation system. This doctoral study has two main contributions, 1) a micropower low-noise neural front-end circuit, and 2) a low-power configurable neural recording system for both neural action-potential (AP) and fast-ripple (FR) signals.
The neural front end consists of a preamplifier followed by a bandpass filter (BPF). This design focuses on improving the noise-power efficiency of the preamplifier and the power/pole merit of the BPF at ultra-low power consumption. In measurement, the preamplifier exhibits 39.6-dB DC gain, 0.8 Hz to 5.2 kHz of bandwidth (BW), 5.86-μVrms input-referred noise in AP mode, while showing 39.4-dB DC gain, 0.36 Hz to 1.3 kHz of BW, 3.07-μVrms noise in FR mode. The preamplifier achieves noise efficiency factor (NEF) of 2.93 and 3.09 for AP and FR modes, respectively. The preamplifier power consumption is 2.4 μW from 2.8 V for both modes. The 6th-order follow-the-leader feedback elliptic BPF passes FR signals and provides -110 dB/decade attenuation to out-of-band interferers. It consumes 2.1 μW from 2.8 V (or 0.35 μW/pole) and is one of the most power-efficient high-order active filters reported to date. The complete front-end circuit achieves a mid-band gain of 38.5 dB, a BW from 250 to 486 Hz, and a total input-referred noise of 2.48 μVrms while consuming 4.5 μW from the 2.8 V power supply. The front-end NEF achieved is 7.6. The power efficiency of the complete front-end is 0.75 μW/pole. The chip is implemented in a standard 0.6-μm CMOS process with a die area of 0.45 mm^2.
The neural recording system incorporates the front-end circuit and a sigma-delta analog-to-digital converter (ADC). The ADC has scalable BW and power consumption for digitizing both AP and FR signals captured by the front end. Various design techniques are applied to the improvement of power and area efficiency for the ADC. At 77-dB dynamic range (DR), the ADC has a peak SNR and SNDR of 75.9 dB and 67 dB, respectively, while consuming 2.75-mW power in AP mode. It achieves 78-dB DR, 76.2-dB peak SNR, 73.2-dB peak SNDR, and 588-μW power consumption in FR mode. Both analog and digital power supply voltages are 2.8 V. The chip is fabricated in a standard 0.6-μm CMOS process. The die size is 11.25 mm^2.
The proposed circuits can be extended to a multi-channel system, with the ADC shared by all channels, as the sensing part of a future closed-loop DBS system for the treatment of intractable epilepsy
Entwurfsregeln für supraleitende Analog-Digital-Wandler
This Thesis is a contribution for dimensioning aspects of circuits
designs in superconductor electronics. Mainly superconductor comparators
inclusive Josephson comparators as well as QOJS-Comparators are investigated. Both types were
investigated in terms of speed and sensitivity. The influence of
the thermal noise on the decision process of the comparators represent
in so called gray zone, which is analysed in this thesis. Thereby,
different relations between design parameters were derived. A circuit
model of the Josephson comparator was verified by experiments.
Concepts of superconductor analog-to-digital converters, which are
based on above called comparators, were investigated in detail. From the
comparator design rules, new rules for AD-converters were derived.
Because of the reduced switching energy, the signal to noise
ratio (SNR) of the circuits is affected and therefore the reliability
of the decision-process is affected. For special applications
with very demanding requirements in terms of the speed and accuracy
superconductor analog-to-digital converters offer an excellent
performance.
This thesis provides relations between different design paramenters and
shows resulting trade-offs, This method is transparent and easy to
transfer to other circuit topologies. As a main result, a highly
predictive tool for dimensioning of superconducing ADC's is proved.Die vorliegende Dissertationsschrift liefert einen Beitrag zu
Dimensionierungsaspekten des Schaltungsentwurfs in der supraleitender
Elektronik.
Dazu werden supraleitende Komparatoren, d. h. Josephson-Komparator und
QOJS-Komparator bezüglich der Geschwindigkeit und der Empfindlichkeit
untersucht. Der Einfluss des thermischen Rauschens auf den
Entscheidungsprozess der Komparatoren repräsentiert die so genannte
Grauzone. Sie wird in der Arbeit als wichtige Kennzahl ausführlich
analysiert. Daraus werden verschiedene Parameterabhängigkeiten
dargestellt. Eine Modellierung eines Josephson-Komparator wurde experimentell
bestätigt.
Darauf aufbauend werden Konzepte von supraleitenden
Analog-Digital-Wandlern in der Arbeit untersucht und daraus
Entwurfsregeln abgeleitet. Durch die Reduzierung der Schaltenegie wird
das Signal-Rausch-Verhältnis (SNR) der Schaltungen und damit
die Zuverlässigkeit von Entscheidungsprozessen und Schaltvorgängen
beeinflusst.
Für Spezialanwendungen mit sehr hohen Anforderungen bezüglich der
Geschwindigkeit oder Genauigkeit bieten supraleitende AD-Wandler
ausgezeichnete Leistungsmerkmale an. Die Arbeit liefert konkrete
Zusammenhänge zwischen den unterschiedlichen Entwurfsparametern und
zeigt mögliche Kompromisse auf. Die Methoden sind transparent
dargestellt und lassen sich leicht auf andere Schaltungstopologien
übertragen.
Im Ergebnis wird ein Werkzeug zur objektiven Dimensionierung von
supraleitenden AD-Wandlern bereitgestellt
Low-voltage low-power continuous-time delta-sigma modulator designs
Ph.DDOCTOR OF PHILOSOPH
Design and implementation of generalized topologies of time-interleaved variable bandpass Σ−Δ modulators
In this thesis, novel analog-to-digital and digital-to-analog generalized time-interleaved variable bandpass sigma-delta modulators are designed, analysed, evaluated and implemented that are suitable for high performance data conversion for a broad-spectrum of applications. These generalized time-interleaved variable bandpass sigma-delta modulators can perform noise-shaping for any centre frequency from DC to Nyquist. The proposed topologies are well-suited for Butterworth, Chebyshev, inverse-Chebyshev and elliptical filters, where designers have the flexibility of specifying the centre frequency, bandwidth as well as the passband and stopband attenuation parameters. The application of the time-interleaving approach, in combination with these bandpass loop-filters, not only overcomes the limitations that are associated with conventional and mid-band resonator-based bandpass sigma-delta modulators, but also offers an elegant means to increase the conversion bandwidth, thereby relaxing the need to use faster or higher-order sigma-delta modulators.
A step-by-step design technique has been developed for the design of time-interleaved variable bandpass sigma-delta modulators. Using this technique, an assortment of lower- and higher-order single- and multi-path generalized A/D variable bandpass sigma-delta modulators were designed, evaluated and compared in terms of their signal-to-noise ratios, hardware complexity, stability, tonality and sensitivity for ideal and non-ideal topologies. Extensive behavioural-level simulations verified that one of the proposed topologies not only used fewer
coefficients but also exhibited greater robustness to non-idealties.
Furthermore, second-, fourth- and sixth-order single- and multi-path digital variable bandpass digital sigma-delta modulators are designed using this technique. The mathematical modelling and evaluation of tones caused by the finite wordlengths of these digital multi-path sigmadelta modulators, when excited by sinusoidal input signals, are also derived from first principles and verified using simulation and experimental results. The fourth-order digital variable-band sigma-delta modulator topologies are implemented in VHDL and synthesized on Xilinx® SpartanTM-3 Development Kit using fixed-point arithmetic. Circuit outputs were taken via RS232 connection provided on the FPGA board and evaluated using MATLAB routines developed by the author. These routines included the decimation process as well. The experiments undertaken by the author further validated the design methodology presented in the work.
In addition, a novel tunable and reconfigurable second-order variable bandpass sigma-delta modulator has been designed and evaluated at the behavioural-level. This topology offers a flexible set of choices for designers and can operate either in single- or dual-mode enabling multi-band implementations on a single digital variable bandpass sigma-delta modulator.
This work is also supported by a novel user-friendly design and evaluation tool that has been developed in MATLAB/Simulink that can speed-up the design, evaluation and comparison of analog and digital single-stage and time-interleaved variable bandpass sigma-delta modulators. This tool enables the user to specify the conversion type, topology, loop-filter type, path number and oversampling ratio