164 research outputs found
Exploiting the bulk-driven approach in CMOS analogue amplifier design
This thesis presents a collection of new novel techniques using the bulk-driven approach, which can lead to performance enhancement in the field of CMOS analogue amplifier design under the very low-supply voltage constraints. In this thesis, three application areas of the bulk-driven approach are focused â at the input-stage of differential pairs, at the source followers, and at the cascode devices.
For the input stage of differential pairs, this thesis proposes two new novel circuit design techniques. One of them utilises the concept of the replica-biased scheme in order to solve the non-linearity and latch-up issues, which are the potential problems that come along with the bulk-driven approach. The other proposed circuit design technique utilises the flipped voltage scheme and the Quasi-Floating Gate technique in order to achieve low-power high-speed performances, and furthermore the reversed-biased diode concept to overcome the issue of degraded input impedance characteristics that come along with the bulk-driven approach. Applying the bulk-driven approach in source followers is a new type of circuit blocks in CMOS analogue field, in which to the authorâs best knowledge has not been proposed at any literatures in the past. This thesis presents the bulk-driven version of the flipped voltage followers and super source followers, which can lead to eliminating the DC level shift. Furthermore, a technique for programming the DC level shift less than the threshold voltage of a MOSFET, which cannot be achieved by conventional types of source followers, is presented.
The effectiveness of the cascode device using the bulk-driven approach is validated by implementing it in a complete schematics design of a fully differential bulk-driven operational transcoductance amplifier (OTA). This proposal leads to solving the lowtranconductance problem of a bulk-driven differential pair, and in effect the open loop gain of
the OTA exceeds 60dB using a 0.35ÎŒm CMOS technology.
The final part of this thesis provides the study result of the input capacitance of a bulk-driven buffer. To verify the use of the BSIM3 MOSFET model in the simulation for predicting the input capacitance, the measurement data of the fabricated device are compared with the postlayout simulation results
Low power output-capacitorless class-AB CMOS LDO regulator
Peer ReviewedPostprint (published version
Low Voltage Low Power Analogue Circuits Design
DisertaÄnĂ prĂĄce je zamÄĆena na vĂœzkum nejbÄĆŸnÄjĆĄĂch metod, kterĂ© se vyuĆŸĂvajĂ pĆi nĂĄvrhu analogovĂœch obvodĆŻ s vyuĆŸitĂ nĂzkonapÄĆ„ovĂœch (LV) a nĂzkopĆĂkonovĂœch (LP) struktur. Tyto LV LP obvody mohou bĂœt vytvoĆeny dĂky vyspÄlĂœm technologiĂm nebo takĂ© vyuĆŸitĂm pokroÄilĂœch technik nĂĄvrhu. DisertaÄnĂ prĂĄce se zabĂœvĂĄ prĂĄvÄ pokroÄilĂœmi technikami nĂĄvrhu, pĆedevĆĄĂm pak nekonvenÄnĂmi. Mezi tyto techniky patĆĂ vyuĆŸitĂ prvkĆŻ s ĆĂzenĂœm substrĂĄtem (bulk-driven - BD), s plovoucĂm hradlem (floating-gate - FG), s kvazi plovoucĂm hradlem (quasi-floating-gate - QFG), s ĆĂzenĂœm substrĂĄtem s plovoucĂm hradlem (bulk-driven floating-gate - BD-FG) a s ĆĂzenĂœm substrĂĄtem s kvazi plovoucĂm hradlem (quasi-floating-gate - BD-QFG). PrĂĄce je takĂ© orientovĂĄna na moĆŸnĂ© zpĆŻsoby implementace znĂĄmĂœch a modernĂch aktivnĂch prvkĆŻ pracujĂcĂch v napÄĆ„ovĂ©m, proudovĂ©m nebo mix-mĂłdu. Mezi tyto prvky lze zaÄlenit zesilovaÄe typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za ĂșÄelem potvrzenĂ funkÄnosti a chovĂĄnĂ vĂœĆĄe zmĂnÄnĂœch struktur a prvkĆŻ byly vytvoĆeny pĆĂklady aplikacĂ, kterĂ© simulujĂ usmÄrĆovacĂ a induktanÄnĂ vlastnosti diody, dĂĄle pak filtry dolnĂ propusti, pĂĄsmovĂ© propusti a takĂ© univerzĂĄlnĂ filtry. VĆĄechny aktivnĂ prvky a pĆĂklady aplikacĂ byly ovÄĆeny pomocĂ PSpice simulacĂ s vyuĆŸitĂm parametrĆŻ technologie 0,18 m TSMC CMOS. Pro ilustraci pĆesnĂ©ho a ĂșÄinnĂ©ho chovĂĄnĂ struktur je v disertaÄnĂ prĂĄci zahrnuto velkĂ© mnoĆŸstvĂ simulaÄnĂch vĂœsledkĆŻ.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the nonâconventional ones which are bulkâdriven (BD), floatingâgate (FG), quasiâfloatingâgate (QFG), bulkâdriven floatingâgate (BDâFG) and bulkâdriven quasiâfloatingâgate (BDâQFG) techniques. The thesis also looks at ways of implementing structures of wellâknown and modern active elements operating in voltageâ, currentâ, and mixedâmode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fullyâdifferential second generation current conveyor (FBâCCII), fullyâbalanced differential difference amplifier (FBâDDA), voltage differencing transconductance amplifier (VDTA), currentâcontrolled current differencing buffered amplifier (CCâCDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diodeâless rectifier and inductance simulations, as well as lowâpass, bandâpass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.
Exploiting the bulk-driven approach in CMOS analogue amplifier design
This thesis presents a collection of new novel techniques using the bulk-driven approach, which can lead to performance enhancement in the field of CMOS analogue amplifier design under the very low-supply voltage constraints. In this thesis, three application areas of the bulk-driven approach are focused â at the input-stage of differential pairs, at the source followers, and at the cascode devices.
For the input stage of differential pairs, this thesis proposes two new novel circuit design techniques. One of them utilises the concept of the replica-biased scheme in order to solve the non-linearity and latch-up issues, which are the potential problems that come along with the bulk-driven approach. The other proposed circuit design technique utilises the flipped voltage scheme and the Quasi-Floating Gate technique in order to achieve low-power high-speed performances, and furthermore the reversed-biased diode concept to overcome the issue of degraded input impedance characteristics that come along with the bulk-driven approach. Applying the bulk-driven approach in source followers is a new type of circuit blocks in CMOS analogue field, in which to the authorâs best knowledge has not been proposed at any literatures in the past. This thesis presents the bulk-driven version of the flipped voltage followers and super source followers, which can lead to eliminating the DC level shift. Furthermore, a technique for programming the DC level shift less than the threshold voltage of a MOSFET, which cannot be achieved by conventional types of source followers, is presented.
The effectiveness of the cascode device using the bulk-driven approach is validated by implementing it in a complete schematics design of a fully differential bulk-driven operational transcoductance amplifier (OTA). This proposal leads to solving the lowtranconductance problem of a bulk-driven differential pair, and in effect the open loop gain of
the OTA exceeds 60dB using a 0.35ÎŒm CMOS technology.
The final part of this thesis provides the study result of the input capacitance of a bulk-driven buffer. To verify the use of the BSIM3 MOSFET model in the simulation for predicting the input capacitance, the measurement data of the fabricated device are compared with the postlayout simulation results
A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design
Designing integrated circuits able to work under low-voltage (LV) low-power (LP) condition is currently undergoing a very considerable boom. Reducing voltage supply and power consumption of integrated circuits is crucial factor since in general it ensures the device reliability, prevents overheating of the circuits and in particular prolongs the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulk-driven (BD), floating-gate (FG) and quasi-floating-gate (QFG) techniques have been proposed as powerful ways to reduce the design complexity and push the voltage supply towards threshold voltage of the MOS transistors (MOST). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application requirements. As an example of application three operational transconductance amplifiers (OTA) base on these non-conventional techniques are presented, the voltage supply is only ±0.4 V and the power consumption is 23.5 ”W. PSpice simulation results using the 0.18 ”m CMOS technology from TSMC are included to verify the design functionality and correspondence with theory
Low-Voltage Analog Circuit Design Using the Adaptively Biased Body-Driven Circuit Technique
The scaling of MOSFET dimensions and power supply voltage, in conjunction with an increase in system- and circuit-level performance requirements, are the most important factors driving the development of new technologies and design techniques for analog and mixed-signal integrated circuits. Though scaling has been a fact of life for analog circuit designers for many years, the approaching 1-V and sub-1-V power supplies, combined with applications that have increasingly divergent technology requirements, means that the analog and mixed-signal IC designs of the future will probably look quite different from those of the past. Foremost among the challenges that analog designers will face in highly scaled technologies are low power supply voltages, which limit dynamic range and even circuit functionality, and ultra-thin gate oxides, which give rise to significant levels of gate leakage current.
The goal of this research is to develop novel analog design techniques which are commensurate with the challenges that designers will face in highly scaled CMOS technologies. To that end, a new and unique body-driven design technique called adaptive gate biasing has been developed. Adaptive gate biasing is a method for guaranteeing that MOSFETs in a body-driven simple current mirror, cascode current mirror, or regulated cascode current source are biased in saturationâindependent of operating region, temperature, or supply voltageâand is an enabling technology for high-performance, low-voltage analog circuits. To prove the usefulness of the new design technique, a body-driven operational amplifier that heavily leverages adaptive gate biasing has been developed. Fabricated on a 3.3-V/0.35-ÎŒm partially depleted silicon-onv-insulator (PD-SOI) CMOS process, which has nMOS and pMOS threshold voltages of 0.65 V and 0.85 V, respectively, the body-driven amplifier displayed an open-loop gain of 88 dB, bandwidth of 9 MHz, and PSRR greater than 50 dB at 1-V power supply
Circuits for Analog Signal Processing Employing Unconventional Active Elements
DisertaÄnĂ prĂĄce se zabĂœvĂĄ zavĂĄdÄnĂm novĂœch struktur modernĂch aktivnĂch prvkĆŻ pracujĂcĂch v napÄĆ„ovĂ©m, proudovĂ©m a smĂĆĄenĂ©m reĆŸimu. FunkÄnost a chovĂĄnĂ tÄchto prvkĆŻ byly ovÄĆeny prostĆednictvĂm SPICE simulacĂ. V tĂ©to prĂĄci je zahrnuta Ćada simulacĂ, kterĂ© dokazujĂ pĆesnost a dobrĂ© vlastnosti tÄchto prvkĆŻ, pĆiÄemĆŸ velkĂœ dĆŻraz byl kladen na to, aby tyto prvky byly schopny pracovat pĆi nĂzkĂ©m napĂĄjecĂm napÄtĂ, jelikoĆŸ poptĂĄvka po pĆenosnĂœch elektronickĂœch zaĆĂzenĂch a implantabilnĂch zdravotnickĂœch pĆĂstrojĂch stĂĄle roste. Tyto pĆĂstroje jsou napĂĄjeny bateriemi a k tomu, aby byla prodlouĆŸena jejich ĆŸivotnost, trend navrhovĂĄnĂ analogovĂœch obvodĆŻ smÄĆuje k stĂĄle vÄtĆĄĂmu sniĆŸovĂĄnĂ spotĆeby a napĂĄjecĂho napÄtĂ. HlavnĂm pĆĂnosem tĂ©to prĂĄce je nĂĄvrh novĂœch CMOS struktur: CCII (Current Conveyor Second Generation) na zĂĄkladÄ BD (Bulk Driven), FG (Floating Gate) a QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) na zĂĄkladÄ FG, transkonduktor na zĂĄkladÄ novĂ© techniky BD_QFG (Bulk Driven_Quasi Floating Gate), CCCDBA (Current Controlled Current Differencing Buffered Amplifier) na zĂĄkladÄ GD (Gate Driven), VDBA (Voltage Differencing Buffered Amplifier) na zĂĄkladÄ GD a DBeTA (Differential_Input Buffered and External Transconductance Amplifier) na zĂĄkladÄ BD. DĂĄle je uvedeno nÄkolik zajĂmavĂœch aplikacĂ uĆŸĂvajĂcĂch vĂœĆĄe jmenovanĂ© prvky. ZĂskanĂ© vĂœsledky simulacĂ odpovĂdajĂ teoretickĂœm pĆedpokladĆŻm.The dissertation thesis deals with implementing new structures of modern active elements working in voltage_, current_, and mixed mode. The functionality and behavior of these elements have been verified by SPICE simulation. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of those elements. However, a big attention to implement active elements by utilizing LV LP (Low Voltage Low Power) techniques is given in this thesis. This attention came from the fact that growing demand of portable electronic equipments and implantable medical devices are pushing the development towards LV LP integrated circuits because of their influence on batteries lifetime. More specifically, the main contribution of this thesis is to implement new CMOS structures of: CCII (Current Conveyor Second Generation) based on BD (Bulk Driven), FG (Floating Gate) and QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) based on FG; Transconductor based on new technique of BD_QFG (Bulk Driven_Quasi Floating Gate); CCCDBA (Current Controlled Current Differencing Buffered Amplifier) based on conventional GD (Gate Driven); VDBA (Voltage Differencing Buffered Amplifier) based on GD. Moreover, defining new active element i.e. DBeTA (Differential_Input Buffered and External Transconductance Amplifier) based on BD is also one of the main contributions of this thesis. To confirm the workability and attractive properties of the proposed circuits many applications were exhibited. The given results agree well with the theoretical anticipation.
An 18GHz Wide-Band Buffer
Recent developments in wireless communication and systems, such as sixth-generation
(6G), radar and instrumentation have led to massive use of high-frequency carriers. As a result,
there is a high demand for Analog-to-Digital Converters (ADCs) in direct-conversion
architectures with high bandwidth, high-resolution, and with the highest possible power
efficiency and spectral purity.
A potential performance enhancement of an ADC can be realized by adding a voltage
Input Buffer (IB). To increase the IB bandwidth and decrease the distortion from the
nonlinear sampling circuit, a low output impedance is required. Therefore, to achieve low
output impedance, it is necessary to dissipate power that is often equal to or greater than
the power dissipated in the rest of the ADC blocks combined, since the output impedance
is inversely proportional to the bias current. Consequently, input buffers are one of the
most "power-hungry" building blocks of any direct receiver chain.
In recent years, due to the high ADC resolution and quantization range, the existing
approaches use IBs with supply voltages above the nominal rails, for instance, 2.5 or 4.0 V,
to increase the linearity and to not limit the ADC output swing. However, it inherently
creates reliability and robustness issues.
This work investigates several different input buffers implemented in 7 nm FinFET
technology with 1.8V of supply voltage in which a one pico farad of sampling capacitance
is driven. The study starts by exploring four single-stage topologies in thick gate devices
with and without linearity techniques, for example, the drain-source voltage "bootstrap"
technique. Moreover, two bandwidth extension techniques are introduced, for instance,
the Bridge T-coil with Series Peaking and the Distributed Approach. Lastly, two-stage IB
architectures with thick oxide devices together with thin oxide devices are implemented.
Finally, the new solutions presented meet the requirements by exhibiting more than
18 GHz of bandwidth with a linearity (IIP3) higher than 16.3 dBm, and a DC power
consumption lower than 178.2 mW without compromising reliability and robustness
issues.Os mais recentes desenvolvimentos nos sistemas de comunicação sem fios, como a sexta
geração (6G) de redes mĂłveis, levaram ao uso massivo de portadoras de alta frequĂȘncia.
Com efeito, Ă© crescente a demanda por conversores analĂłgico-digital (ADCs) nas arquiteturas
de conversão direta, com elevada largura de banda, de alta resolução, com um baixo
consumo de energia e com uma elevada linearidade.
Uma potencial melhoria no desempenho do ADC pode ser alcançada através de
um input buffer (IB). Para aumentar a largura de banda do IB e diminuir a distorção
causada pelo circuito de amostragem Ă© necessĂĄria uma baixa impedĂąncia de saĂda. Sendo
a impedĂąncia de saĂda inversamente proporcional Ă corrente de polarização, para alcançar
umaimpedĂąncia de saĂda baixa Ă© essencial dissiparpotĂȘncia que muitas das vezes Ă© igualou
superior Ă soma da potĂȘncia consumida no resto dos blocos do ADC. Consequentemente,
o input buffer Ă© um dos blocos da cadeia recetora que mais energia consume.
Nos Ășltimos anos, devido Ă elevada resolução do ADC, as abordagens existentes usam
input buffers com tensÔes de alimentação superiores à tensão nominal de alimentação, por
exemplo, 2.5 ou 4.0 V, de forma a aumentar a linearidade e nĂŁo limitar a tensĂŁo saĂda do
ADC. Porém, inerentemente surgem questÔes de fiabilidade e robustez.
Neste contexto, o escopo do presente trabalho Ă© investigar diversos input buffers implementados
em tecnologia 7 nm FinFET com 1.8V de tensão de alimentação e com uma
capacidade de carga de um pico farad. O estudo começa por explorar quatro topologias
de input buffer com dispositivos de grandes dimensÔes, com e sem técnicas de linearidade,
nomeadamente, a técnica que força a tensão dreno-fonte a ser constante. Ademais, são
introduzidas duas técnicas que aumentam a largura de banda, The Bridge T-coil com Series
Peaking e a Distributed Approach. Finalmente, sĂŁo implementadas arquiteturas de input
buffer com dois andares em dispositivos de pequenas e grandes dimensÔes.
Por Ășltimo, sĂŁo apresentadas novas soluçÔes que cumprem inteiramente as especificaçÔes,
uma vez que exibem uma largura de banda maior que 18 GHz com uma linearidade
(IIP3) superior 16.3 dBm e um consumo de potĂȘncia inferior a 178.2mW, sem comprometer
a fiabilidade e a robustez dos dispositivos
Utilizing Unconventional CMOS Techniques for Low Voltage Low Power Analog Circuits Design for Biomedical Applications
Tato disertaÄnĂ prĂĄce se zabĂœvĂĄ navrĆŸenĂm nĂzkonapÄĆ„ovĂœch, nĂzkopĆĂkonovĂœch analogovĂœch obvodĆŻ, kterĂ© pouĆŸĂvajĂ nekonvenÄnĂ techniky CMOS. LĂ©kaĆskĂĄ zaĆĂzenĂ na bateriovĂ© napĂĄjenĂ, jako systĂ©my pro dlouhodobĂœ fyziologickĂœ monitoring, pĆenosnĂ© systĂ©my, implantovatelnĂ© systĂ©my a systĂ©my vhodnĂ© na noĆĄenĂ, musĂ bĂœt male a lehkĂ©. KromÄ toho je nutnĂ©, aby byly tyto systĂ©my vybaveny bateriĂ s dlouhou ĆŸivotnostĂ. Z tohoto dĆŻvodu pĆevlĂĄdajĂ v biomedicĂnskĂœch aplikacĂch tohoto typu nĂzkopĆĂkonovĂ© integrovanĂ© obvody. NekonvenÄnĂ techniky jako napĆ. vyuĆŸitĂ transistorĆŻ s ĆĂzenĂœm substrĂĄtem (Bulk-Driven âBDâ), s plovoucĂm hradlem (Floating-Gate âFGâ), s kvazi plovoucĂm hradlem (Quasi-Floating-Gate âQFGâ), s ĆĂzenĂœm substrĂĄtem s plovoucĂm hradlem (Bulk-Driven Floating-Gate âBD-FGâ) a s ĆĂzenĂœm substrĂĄtem s kvazi plovoucĂm hradlem (Bulk-Driven Quasi-Floating-Gate âBD-QFGâ), se v nedĂĄvnĂ© dobÄ ukĂĄzaly jako efektivnĂ prostĆedek ke zjednoduĆĄenĂ obvodovĂ©ho zapojenĂ a ke snĂĆŸenĂ velikosti napĂĄjecĂho napÄtĂ smÄrem k prahovĂ©mu napÄtĂ u tranzistorĆŻ MOS (MOST). V prĂĄci jsou podrobnÄ pĆedstaveny nejdĆŻleĆŸitÄjĆĄĂ charakteristiky nekonvenÄnĂch technik CMOS. Tyto techniky byly pouĆŸity pro vytvoĆenĂ nĂzko napÄĆ„ovĂœch a nĂzko vĂœkonovĂœch CMOS struktur u nÄkterĂœch aktivnĂch prvkĆŻ, napĆ. Operational Transconductance Amplifier (OTA) zaloĆŸenĂ© na BD, FG, QFG, a BD-QFG techniky; Tunable Transconductor zaloĆŸenĂœ na BD MOST; Current Conveyor Transconductance Amplifier (CCTA) zaloĆŸenĂœ na BD-QFG MOST; Z Copy-Current Controlled-Current Differencing Buffered Amplifier (ZC-CC-CDBA) zaloĆŸenĂœ na BD MOST; Winner Take All (WTA) and Loser Take All (LTA) zaloĆŸenĂœ na BD MOST; Fully Balanced Four-Terminal Floating Nullor (FBFTFN) zaloĆŸenĂœ na BD-QFG technice. Za ĂșÄelem ovÄĆenĂ funkÄnosti vĂœĆĄe zmĂnÄnĂœch struktur, byly tyto struktury pouĆŸity v nÄkolika aplikacĂch. VĂœkon navrĆŸenĂœch aktivnĂch prvkĆŻ a pĆĂkladech aplikacĂ je ovÄĆovĂĄn prostĆednictvĂm simulaÄnĂch programĆŻ PSpice Äi Cadence za pouĆŸitĂ technologie 0.18 m CMOS.This doctoral thesis deals with designing ultra-low-voltage (LV) low-power (LP) analog circuits utilizing the unconventional CMOS techniques. Battery powered medical devices such as; long term physiological monitoring, portable, implantable, and wearable systems need to be small and lightweight. Besides, long life battery is essential need for these devices. Thus, low-power integrated circuits are always paramount in such biomedical applications. Recently, unconventional CMOS techniques i.e. Bulk-Driven (BD), Floating-Gate (FG), Quasi-Floating-Gate (QFG), Bulk-Driven Floating-Gate (BD-FG) and Bulk-Driven Quasi-Floating-Gate (BD-QFG) MOS transistors (MOSTs) have revealed as effective devices to reduce the circuit complexity and push the voltage supply of the circuit towards threshold voltage of the MOST. In this work, the most important features of the unconventional CMOS techniques are discussed in details. These techniques have been utilized to perform ultra-LV LP CMOS structures of several active elements i.e. Operational Transconductance Amplifier (OTA) based on BD, FG, QFG, and BD-QFG techniques; Tunable Transconductor based on BD MOST; Current Conveyor Transconductance Amplifier (CCTA) based on BD-QFG MOST; Z Copy-Current Controlled-Current Differencing Buffered Amplifier (ZC-CC-CDBA) based on BD MOST; Winner Take All (WTA) and Loser Take All (LTA) based on BD MOST; Fully Balanced Four-Terminal Floating Nullor (FBFTFN) based on BD-QFG technique. Moreover, to verify the workability of the proposed structures, they were employed in several applications. The performance of the proposed active elements and their applications were investigated through PSpice or Cadence simulation program using 0.18 m CMOS technology.
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