A Concurrent Dual-Band Inverter-Based Low Noise Amplifier (LNA) for WLAN Applications

low noise amplifier (LNA); concurrent; dual-band; inverter-basedIn this paper, a two-stage concurrent dual-band low noise amplifier (DB-LNA) operating at 2.4/5.2-GHz is presented for Wireless Local Area Network (WLAN) applications. The current-reused structure using resistive shunt-shunt feedback is employed to reduce power dissipation and achieve a wide frequency band from DC to-5.5-GHz in the inverter-based LNA. The second inverter-based stage is employed to increase the gain and obtain a flat gain over the frequency band. An LC network is also inserted at the proposed circuit output to shape the dual-band frequency response. The proposed concurrent DB-LNA is designed by RF-TSMC 0.18-µm CMOS technology, which consumes 10.8 mW from a power supply of 1.5 V. The simulation results show that the proposed DB-LNA achieves a direct power gain (S 21 ) of 13.7/14.1 dB, a noise figure (NF) of 4.2/4.6 dB, and an input return loss (S 11 ) of −12.9/−14.6 dBm at the 2.4/5.2-GHz bands

A Q-enhanced 3.6 GHz tunable CMOS bandpass filter for wideband wireless applications

With the rapid development of information technology, more and more bandwidth is required to transmit multimedia data. Since local communication networks are moving to wireless domain, it brings up great challenges for making integrated wideband wireless front-ends suitable for these applications. RF filtering is a fundamental need in all wireless front-ends and is one of the most difficult parts to be integrated. This has been a major obstacle to the implementation of low power and low cost integrated wireless terminals. Lots of previous work has been done to make integrated RF filters applicable to these applications. However, some of these filters are not designed with standard CMOS technology. Some of them are not designed in desired frequency bands and others do not have sufficient frequency bandwidth. This research demonstrates the design of a tunable wideband RF filter that operates at 3.6 GHz and can be easily changed to a higher frequency range up to 5 GHz. This filter is superior to the previous designs in the following aspects: a) wider bandwidth, b) easier to tune, c) balancing in noise and linearity, and d) using standard CMOS technology. The design employs the state-of-the-art inductor degenerated LNA, acting as a transconductor to minimize the overall noise figure. A Q-enhancement circuit is employed to compensate the loss from lossy on-chip spiral inductors. Center frequency and bandwidth tuning circuits are also embedded to make the filter suitable for multi band operations. At first, a second order bandpass filter prototype was designed in the standard 0.18 ìm CMOS process. Simulation results showed that at 3.6 GHz center frequency and with a 60-MHz bandwidth, the input third-order intermodulation product (IIP3) and input-referred 1 dB compression point (P1dB) was -22.5 dBm and -30.5 dBm respectively. The image rejection at 500 MHz away from the center frequency was 32 dB (250 MHz intermediate frequency). The Q of the filter was tunable over 3000 and the center frequency tuning range was about 150 MHz. By cascading three stages of second order filters, a sixth order filter was designed to enhance the image rejection ability and to extend the filter bandwidth. The sixth order filter had been fabricated in the standard 0.18 ìm CMOS process using 1.8-V supply. The chip occupies only 0.9 mm 0.9 mm silicon area and has a power consumption of 130-mW. The measured center frequency was tunable from 3.54 GHz to 3.88 GHz, bandwidth was tunable from 35 MHz to 80 MHz. With a 65 MHz bandwidth, the filter had a gain of 13 dB, an IIP3 of -29 dBm and a P1dB of -46 dBm

Survey on individual components for a 5 GHz receiver system using 130 nm CMOS technology

La intención de esta tesis es recopilar información desde un punto de vista general sobre los diferentes tipos de componentes utilizados en un receptor de señales a 5 GHz utilizando tecnología CMOS. Se ha realizado una descripción y análisis de cada uno de los componentes que forman el sistema, destacando diferentes tipos de configuraciones, figuras de mérito y otros parámetros. Se muestra una tabla resumen al final de cada sección, comparando algunos diseños que se han ido presentando a lo largo de los años en conferencias internacionales de la IEEE.The intention of this thesis is to gather information from an overview point about the different types of components used in a 5 GHz receiver using CMOS technology. A review of each of the components that form the system has been made, highlighting different types of configurations, figure of merits and parameters. A summary table is shown at the end of each section, comparing many designs that have been presented over the years at international conferences of the IEEE.Departamento de Ingeniería Energética y FluidomecánicaGrado en Ingeniería en Electrónica Industrial y Automátic

A dual-mode Q-enhanced RF front-end filter for 5 GHz WLAN and UWB with NB interference rejection

The 5 GHz Wireless LAN (802.11a) is a popular standard for wireless indoor communications providing moderate range and speed. Combined with the emerging ultra Wideband standard (UWB) for short range and high speed communications, the two standards promise to fulfil all areas of wireless application needs. However, due to the overlapping of the two spectrums, the stronger 802.11a signals tend to interfere causing degradation to the UWB receiver. This presents one of the main technical challenges preventing the wide acceptance of UWB. The research work presented in this thesis is to propose a low cost RF receiver front-end filter topology that would resolve the narrowband (NB) interference to UWB receiver while being operable in both 802.11a mode and UWB mode. The goal of the dual mode filter design is to reduce cost and complexity by developing a fully integrated front-end filter. The filter design utilizes high Q passive devices and Q-enhancement technique to provide front-end channel-selection in NB mode and NB interference rejection in UWB mode. In the 802.11a NB mode, the filter has a tunable gain of 4 dB to 25 dB, NF of 8 dB and an IIP3 between -47 dBm and -18 dBm. The input impedance is matched at -16 dB. The frequency of operation can be tuned from 5.15 GHz to 5.35 GHz. In the UWB mode, the filter has a gain of 0 dB to 8 dB across 3.1 GHz to 9 GHz. The filter can reject the NB interference between 5.15 GHz to 5.35 GHz at up to 60 dB. The Q of the filter is tunable up to a 250 while consuming a maximum of 23.4 mW of power. The fully integrated dual mode filter occupies a die area of 1.1 mm2

Ultra-Low Power Wake Up Receiver For Medical Implant Communications Service Transceiver

This thesis explores the specific requirements and challenges for the design of a dedicated wake-up receiver for medical implant communication services equipped with a novel “uncertain-IF†architecture combined with a high – Q filtering MEMS resonator and a free running CMOS ring oscillator as the RF LO. The receiver prototype, implements an IBM 0.18μm mixed-signal 7ML RF CMOS technology and achieves a sensitivity of -62 dBm at 404MHz while consuming \u3c100 μW from a 1 V supply

Passive and active circuits in cmos technology for rf, microwave and millimeter wave applications

The permeation of CMOS technology to radio frequencies and beyond has fuelled an urgent need for a diverse array of passive and active circuits that address the challenges of rapidly emerging wireless applications. While traditional analog based design approaches satisfy some applications, the stringent requirements of newly emerging applications cannot necessarily be addressed by existing design ideas and compel designers to pursue alternatives. One such alternative, an amalgamation of microwave and analog design techniques, is pursued in this work. A number of passive and active circuits have been designed using a combination of microwave and analog design techniques. For passives, the most crucial challenge to their CMOS implementation is identified as their large dimensions that are not compatible with CMOS technology. To address this issue, several design techniques – including multi-layered design and slow wave structures – are proposed and demonstrated through experimental results after being suitably tailored for CMOS technology. A number of novel passive structures - including a compact 10 GHz hairpin resonator, a broadband, low loss 25-35 GHz Lange coupler, a 25-35 GHz thin film microstrip (TFMS) ring hybrid, an array of 0.8 nH and 0.4 nH multi-layered high self resonant frequency (SRF) inductors are proposed, designed and experimentally verified. A number of active circuits are also designed and notable experimental results are presented. These include 3-10 GHz and DC-20 GHz distributed low noise amplifiers (LNA), a dual wideband Low noise amplifier and 15 GHz distributed voltage controlled oscillators (DVCO). Distributed amplifiers are identified as particularly effective in the development of wideband receiver front end sub-systems due to their gain flatness, excellent matching and high linearity. The most important challenge to the implementation of distributed amplifiers in CMOS RFICs is identified as the issue of their miniaturization. This problem is solved by using integrated multi-layered inductors instead of transmission lines to achieve over 90% size compression compared to earlier CMOS implementations. Finally, a dual wideband receiver front end sub-system is designed employing the miniaturized distributed amplifier with resonant loads and integrated with a double balanced Gilbert cell mixer to perform dual band operation. The receiver front end measured results show 15 dB conversion gain, and a 1-dB compression point of -4.1 dBm in the centre of band 1 (from 3.1 to 5.0 GHz) and -5.2 dBm in the centre of band 2 (from 5.8 to 8 GHz) with input return loss less than 10 dB throughout the two bands of operation

A Fully Integrated CMOS Receiver.

The rapidly growing wireless communication market is creating an increasing demand for low-cost highly-integrated radio frequency (RF) communication systems. This dissertation focuses on techniques to enable fully-integrated, wireless receivers incorporating all passive components, including the antenna, and also incorporating baseband synchronization on-chip. Not only is the receiver small in size and requires very low power, but it also delivers synchronized demodulated data. This research targets applications such as implantable neuroprosthetic devices and environmental wireless sensors, which need short range, low data-rate wireless communications but a long lifetime. To achieve these goals, the super-regenerative architecture is used, since power consumption with this architecture is low due to the simplified receiver architecture. This dissertation presents a 5GHz single chip receiver incorporating a compact on-chip 5 GHz slot antenna (50 times smaller than traditional dipole antennas) and a digital received data synchronization. A compact capacitively-loaded 5 GHz standing-wave resonator is used to improve the energy efficiency. An all-digital PLL timing scheme synchronizes the received data clock. A new type of low-power envelope detector is incorporated to increase the data rate and efficiency. The receiver achieves a data rate up to 1.2 Mb/s, dissipates 6.6 mW from a 1.5 V supply. The novel on-chip capacitively-loaded, transmission-line-standing-wave resonator is employed instead of a conventional low-Q on-chip inductor. The simulated quality factor of the resonator is very high (35), and is verified by phase-noise measurements of a prototype 5GHz Voltage Control Oscillator (VCO) incorporating this resonator. The prototype VCO, implemented in 0.13 µm CMOS, dissipates 3 mW from a 1.2 V supply, and achieves a measured phase noise of -117 dBc/Hz at a 1 MHz offset. In the on-chip antenna an efficient shielding technique is used to shield the antenna from the low-resistivity substrate underneath. Two standalone on-chip slot antenna prototypes were designed and fabricated in 0.13 µm CMOS. The 9 GHz prototype occupies a die area of only 0.3 mm2, has an active gain of -4.4 dBi and an efficiency of 9%. The second prototype occupies a die area of 0.47 mm2, and achieves a passive gain of approximately -17.0 dBi at 5 GHz.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/60739/1/shid_1.pd

Advanced Trends in Wireless Communications

Physical limitations on wireless communication channels impose huge challenges to reliable communication. Bandwidth limitations, propagation loss, noise and interference make the wireless channel a narrow pipe that does not readily accommodate rapid flow of data. Thus, researches aim to design systems that are suitable to operate in such channels, in order to have high performance quality of service. Also, the mobility of the communication systems requires further investigations to reduce the complexity and the power consumption of the receiver. This book aims to provide highlights of the current research in the field of wireless communications. The subjects discussed are very valuable to communication researchers rather than researchers in the wireless related areas. The book chapters cover a wide range of wireless communication topics

Low noise amplifier design and noise cancellation for wireless hearing aids

Master'sMASTER OF ENGINEERIN

Low complexity blind and data-aided IQ imbalance compensation methods for low-IF receivers

Low-IF and Zero-IF (direct conversion) down converters showed a great potential in implementing multi standard single chip solutions, eliminating the need to use off chip components and so reduce the area and the cost of the wireless receivers. One of the main performance limitations in the low-IF & Zero-IF down-converters is the components mismatch between the in-phase path and the quadrature-path named the IQ Imbalance (IQI) which limits the achievable image rejection ratio (IRR) of the down converters. Many techniques had been proposed to enhance the achievable IRR either by using calibration methods, e.g. using lab calibration, or by doing online compensation during signal reception. In this work those techniques are reviewed, proposing three new methods for blind IQI compensation techniques, the first proposed method targets the low input signal to interference ratio (low SIRin) while the second and third methods targets the moderate and high SIRin, showing that the proposed methods reach better performance and/or lower complexity than the methods already introduced in the literature. Also two techniques to perform data aided IQI compensation are introduced exploiting pilot symbols within the desired signal with no prior knowledge about the image signal. The first method exploits a preamble sequence assuming slow fading condition while the second approach exploits a sequence of pilots to compensate for the IQI being suitable for fast fading conditions as well. Simulation results showed that the proposed data aided techniques achieved shorter convergence time and higher image rejection ratio compared to the blind methods at high SNR values