Transmitter and Receiver Circuits for a High-Speed Polymer Fiber-Based PAM-4 Communication Link

A high data rate RF-DAC and a power detector (PD) are designed and fabricated in a 250 nm indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. A communication link using the Tx-Rx over polymer microwave fiber (PMF) is measured. The link consists of a pulse amplitude modulation (PAM) modulator and a PD as a demodulator, as well as a one-meter-long dielectric waveguide. The working frequency range of the complete link is verified to be 110–150 GHz. The peak output power of the PAM modulator is 5 dBm, and it has a −3 dB bandwidth of 43 GHz. The PD consists of a parallel connected common emitter configured transistor and a common base configured transistor to suppress the odd-order harmonics at the PD’s output, as well as a stacked transistor to amplify the output signal. Tx and Rx chips, including pads, occupy a total area of only 0.83 mm2. The PMF link can support a PAM-4 signal with 22 Gbps data transmission, and a PAM-2 signal with 30 Gbps data transmission, with a bit error rate (BER) of <10−12, with demodulation performed in real time. Furthermore, the energy efficiency for the link (Tx + Rx) is 4.1 pJ/bit, using digital data input and receiving PAM-2 output (5.6 pJ/bit for PAM-4)

Architectures de contrôleurs ultra-faible consommation pour noeuds de réseau de capteurs sans fil

National audienceCet article traite de la conception d'architectures de contrôle pour les noeuds d'un réseau de capteurs. En utilisant conjointement la spécialisation du matériel pour réduire la consommation dynamique et la coupure d'alimentation pour les phases de veille, nous proposons un paradigme d'architecture original ainsi que son flot de conception fonctionnel depuis des spécifications de haut-niveau (langage C associé à un langage spécifiquement conçu). Nous illustrons les gains apportés par un flot complet de génération de micro-tâches matérielles par rapport à des implantations logicielles classiques ciblant des micro-contrôleurs. En combinant la spécialisation matérielle avec des techniques de réduction de puissance statique (power gating), nous réduisons de façon très significative la puissance globale (et l'énergie) dissipée par le système. Les résultats sur des benchmarks issus du domaine des réseaux de capteurs montrent des gains en énergie allant jusqu'à deux ordres de grandeur par rapport aux meilleurs micro-contrôleurs faible consommation du domaine

A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation

There is an increasingly higher number of mixed-signal circuits within microprocessors and systems on chip (SoC). A significant portion of them corresponds to high-speed input/output (HSIO) links. Post-silicon validation of HSIO links can be critical for making a product release qualification decision under aggressive launch schedules. The optimization of receiver analog circuitry in modern HSIO links is a very time consuming post-silicon validation process. Current industrial practices are based on exhaustive enumeration methods to improve either the system margins or the jitter tolerance compliance test. In this paper, these two requirements are addressed in a holistic optimization-based approach. We propose a novel objective function based on these two metrics. Our method employs Kriging to build a surrogate model based on system margining and jitter tolerance measurements. The proposed method, tested with three different realistic server HSIO links, is able to deliver optimal system margins and guarantee jitter tolerance compliance while substantially decreasing the typical post-silicon validation time.ITESO, A.C

The Importance of Implementing Cyber Physical Systems to Acquire Real-Time Data and Indicators

Among the new trends in technology that have emerged through the Industry 4.0, Cyber Physical Systems (CPS) and Internet of Things (IoT) are crucial for the real-time data acquisition. This data acquisition, together with its transformation in valuable information, are indispensable for the development of real-time indicators. Moreover, real-time indicators provide companies with a competitive advantage over the competition since they enhance the calculus and speed up the decision-making and failure detection. Our research highlights the advantages of real-time data acquisition for supply chains, developing indicators that would be impossible to achieve with traditional systems, improving the accuracy of the existing ones and enhancing the real-time decision-making. Moreover, it brings out the importance of integrating technologies 4.0 in industry, in this case, CPS and IoT, and establishes the main points for a future research agenda of this topic.This research received no external fundin

Optimization and Control of Cyber-Physical Vehicle Systems

A cyber-physical system (CPS) is composed of tightly-integrated computation, communication and physical elements. Medical devices, buildings, mobile devices, robots, transportation and energy systems can benefit from CPS co-design and optimization techniques. Cyber-physical vehicle systems (CPVSs) are rapidly advancing due to progress in real-time computing, control and artificial intelligence. Multidisciplinary or multi-objective design optimization maximizes CPS efficiency, capability and safety, while online regulation enables the vehicle to be responsive to disturbances, modeling errors and uncertainties. CPVS optimization occurs at design-time and at run-time. This paper surveys the run-time cooperative optimization or co-optimization of cyber and physical systems, which have historically been considered separately. A run-time CPVS is also cooperatively regulated or co-regulated when cyber and physical resources are utilized in a manner that is responsive to both cyber and physical system requirements. This paper surveys research that considers both cyber and physical resources in co-optimization and co-regulation schemes with applications to mobile robotic and vehicle systems. Time-varying sampling patterns, sensor scheduling, anytime control, feedback scheduling, task and motion planning and resource sharing are examined

Architectures de contrôleurs ultra-faible consommation pour noeuds de réseau de capteurs sans fil

National audienceCet article traite de la conception d'architectures de contrôle pour les noeuds d'un réseau de capteurs. En utilisant conjointement la spécialisation du matériel pour réduire la consommation dynamique et la coupure d'alimentation pour les phases de veille, nous proposons un paradigme d'architecture original ainsi que son flot de conception fonctionnel depuis des spécifications de haut-niveau (langage C associé à un langage spécifiquement conçu). Nous illustrons les gains apportés par un flot complet de génération de micro-tâches matérielles par rapport à des implantations logicielles classiques ciblant des micro-contrôleurs. En combinant la spécialisation matérielle avec des techniques de réduction de puissance statique (power gating), nous réduisons de façon très significative la puissance globale (et l'énergie) dissipée par le système. Les résultats sur des benchmarks issus du domaine des réseaux de capteurs montrent des gains en énergie allant jusqu'à deux ordres de grandeur par rapport aux meilleurs micro-contrôleurs faible consommation du domaine

Bibliographical review on cyber attacks from a control oriented perspective

This paper presents a bibliographical review of definitions, classifications and applications concerning cyber attacks in networked control systems (NCSs) and cyber-physical systems (CPSs). This review tackles the topic from a control-oriented perspective, which is complementary to information or communication ones. After motivating the importance of developing new methods for attack detection and secure control, this review presents security objectives, attack modeling, and a characterization of considered attacks and threats presenting the detection mechanisms and remedial actions. In order to show the properties of each attack, as well as to provide some deeper insight into possible defense mechanisms, examples available in the literature are discussed. Finally, open research issues and paths are presented.Peer ReviewedPostprint (author's final draft

Multilevel simulation-based co-design of next generation HPC microprocessors

This paper demonstrates the combined use of three simulation tools in support of a co-design methodology for an HPC-focused System-on-a-Chip (SoC) design. The simulation tools make different trade-offs between simulation speed, accuracy and model abstraction level, and are shown to be complementary. We apply the MUSA trace-based simulator for the initial sizing of vector register length, system-level cache (SLC) size and memory bandwidth. It has proven to be very efficient at pruning the design space, as its models enable sufficient accuracy without having to resort to highly detailed simulations. Then we apply gem5, a cycle-accurate micro-architecture simulator, for a more refined analysis of the performance potential of our reference SoC architecture, with models able to capture detailed hardware behavior at the cost of simulation speed. Furthermore, we study the network-on-chip (NoC) topology and IP placements using both gem5 for representative small- to medium-scale configurations and SESAM/VPSim, a transaction-level emulator for larger scale systems with good simulation speed and sufficient architectural details. Overall, we consider several system design concerns, such as processor subsystem sizing and NoC settings. We apply the selected simulation tools, focusing on different levels of abstraction, to study several configurations with various design concerns and evaluate them to guide architectural design and optimization decisions. Performance analysis is carried out with a number of representative benchmarks. The obtained numerical results provide guidance and hints to designers regarding SIMD instruction width, SLC sizing, memory bandwidth as well as the best placement of memory controllers and NoC form factor. Thus, we provide critical insights for efficient design of future HPC microprocessors.This work has been performed in the context of the European Processor Initiative (EPI) project, which has received funding from the European Union’s Horizon 2020 research and innovation program under Grant Agreement № 826647. A special thanks to Amir Charif and Arief Wicaksana for their invaluable contributions to the SESAM/VPSim tool in the initial phases of the EPI project.Peer ReviewedPostprint (author's final draft

Az agrárdigitalizáció elterjedését segítő kutatási irányok és lehetőségek

A digitalizáció és az automatizáció nélkül manapság nem lehet versenyelőnyre szert tenni a mostani piaci helyzetben, és ez igaz a mezőgazdaságra is. A technológiai fejlődés lehetővé teszi, hogy olyan módszereket, gépeket, precíziós eszközöket és folyamatokat lehessen alkalmazni az agrárium területén, amely csökkenti a termelési költségeket és a környezetre gyakorolt negatív hatást. A költségek mérséklésével a gazdálkodók növelni tudják a termelést, annak ellenére, hogy a munkaerőpiac erőforráshiánnyal küzd, amely igaz a mezőgazdaság területére is. A megjelenő kihívásokra, mint pl. az éghajlatváltozásra, a szigorú élelmezés- és táplálkozásbiztonsági előírásokra, valamint a megváltozott fogyasztói igényekre a technológia adta lehetőségek kihasználásával lehet választ adni. A gazdálkodóknak ehhez kész megoldásokra van szükségük, amelyeknek alapját az exponenciális mértékben előálló adatok adják. Az adatokat a termelők rendelkezésére szükséges bocsátani szolgáltatások formájában, támogatva ezzel a hatékonyabb döntéshozatalt. Ez a megoldás létezhet közösségi megvalósulás keretei között is, ahol a gazdálkodói közösségen belül nagyobb a bizalom, mint a piaci alapon működő technológiai megoldásokkal szemben. Nem elég megteremteni hozzá a megfelelő adatkörnyezetet és a használható szolgáltatást, hanem még fontos áthidalni a generációs különbségeket és az alacsony digitális készség problémáit is. Ehhez viszont elengedhetetlen egy nonprofit módon működő adatkörnyezet létrehozása, amely gyűjti az adatokat a gazdálkodási értéklánc során használt digitális eszközökből, majd mindezt a gazdálkodók számára bocsátja felhasználásra szolgáltatások formájában. Ennek segítségével megfelelőbb gazdálkodási döntéseket tud hozni. A holisztikus és nyílt rendszerű gondolkodás létfontosságú a sikeres és fenntartható agrárium terén

Schedulability Analysis for Multi-Core Systems Accounting for Resource Stress and Sensitivity

Timing verification of multi-core systems is complicated by contention for shared hardware resources between co-running tasks on different cores. This paper introduces the Multi-core Resource Stress and Sensitivity (MRSS) task model that characterizes how much stress each task places on resources and how much it is sensitive to such resource stress. This model facilitates a separation of concerns, thus retaining the advantages of the traditional two-step approach to timing verification (i.e. timing analysis followed by schedulability analysis). Response time analysis is derived for the MRSS task model, providing efficient context-dependent and context independent schedulability tests for both fixed priority preemptive and fixed priority non-preemptive scheduling. Dominance relations are derived between the tests, and proofs of optimal priority assignment provided. The MRSS task model is underpinned by a proof-of-concept industrial case study