13 research outputs found
Electrical Test of Resistive and Capacitive Open Defects at Data Bus in 3D Memory IC
We propose an electrical test method of resistive and capacitive open defects occurring at data bus lines between dies, and between dies and I/O pins in 3D memory ICs. The test method is based on supply current of an IC. The number of test vectors for a 3D memory IC made of ND memory dies in the test method is 10∙ND and small. Also, defective interconnects are located by the test method. Feasibility of the tests is examined by some experiments for a circuit made of an SRAM IC on a printed circuit board. The experimental results show that capacitive open defects and resistive open ones whose resistance values are greater than 200Ω can be detected by the test method
Reliability Analysis of Electrotechnical Devices
This is a book on the practical approaches of reliability to electrotechnical devices and systems. It includes the electromagnetic effect, radiation effect, environmental effect, and the impact of the manufacturing process on electronic materials, devices, and boards
Multiscale microstructures and microstructural effects on the reliability of microbumps in three-dimensional integration
The dimensions of microbumps in three-dimensional integration reach microscopic scales and thus necessitate a study of the multiscale microstructures in microbumps. Here, we present simulated mesoscale and atomic-scale microstructures of microbumps using phase field and phase field crystal models. Coupled microstructure, mechanical stress, and electromigration modeling was performed to highlight the microstructural effects on the reliability of microbumps. The results suggest that the size and geometry of microbumps can influence both the mesoscale and atomic-scale microstructural formation during solidification. An external stress imposed on the microbump can cause ordered phase growth along the boundaries of the microbump. Mesoscale microstructures formed in the microbumps from solidification, solid state phase separation, and coarsening processes suggest that the microstructures in smaller microbumps are more heterogeneous. Due to the differences in microstructures, the von Mises stress distributions in microbumps of different sizes and geometries vary. In addition, a combined effect resulting from the connectivity of the phase morphology and the amount of interface present in the mesoscale microstructure can influence the electromigration reliability of microbumps
Heterogeneous 2.5D integration on through silicon interposer
© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity
Multiscale microstructures and microstructural effects on the reliability of microbumps in three-dimensional integration
The dimensions of microbumps in three-dimensional integration reach microscopic scales and thus necessitate a study of the multiscale microstructures in microbumps. Here, we present simulated mesoscale and atomic-scale microstructures of microbumps using phase field and phase field crystal models. Coupled microstructure, mechanical stress, and electromigration modeling was performed to highlight the microstructural effects on the reliability of microbumps. The results suggest that the size and geometry of microbumps can influence both the mesoscale and atomic-scale microstructural formation during solidification. An external stress imposed on the microbump can cause ordered phase growth along the boundaries of the microbump. Mesoscale microstructures formed in the microbumps from solidification, solid state phase separation, and coarsening processes suggest that the microstructures in smaller microbumps are more heterogeneous. Due to the differences in microstructures, the von Mises stress distributions in microbumps of different sizes and geometries vary. In addition, a combined effect resulting from the connectivity of the phase morphology and the amount of interface present in the mesoscale microstructure can influence the electromigration reliability of microbumps
3D modeling and integration of current and future interconnect technologies
Title from PDF of title page viewed June 21, 2021Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 133-138)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2021To ensure maximum circuit reliability it is very important to estimate the circuit
performance and signal integrity in the circuit design phase. A full phase simulation for
performance estimation of a large-scale circuit not only require a massive computational
resource but also need a lot of time to produce acceptable results. The estimation of
performance/signal integrity of sub-nanometer circuits mostly depends on the interconnect
capacitance. So, an accurate model for interconnect capacitance can be used in the circuit
CAD (computer-aided design) tools for circuit performance estimation before circuit
fabrication which reduces the computational resource requirement as well as the time
constraints. We propose a new capacitance models for interconnect lines in multilevel
interconnect structures by geometrically modeling the electrical flux lines of the interconnect
lines. Closed-form equations have been derived analytically for ground and coupling
capacitance. First, the capacitance model for a single line is developed, and then the new
model is used to derive expressions for the capacitance of a line surrounded by neighboring
lines in the same and the adjacent layers above and below. These expressions are simple, and
the calculated results are within 10% of Ansys Q3D extracted values.
Through silicon via (TSV) is one of the key components of the emerging 3D ICs.
However, increasing number of TSVs in smaller silicon area leads to some severe negative
impacts on the performance of the 3D IC. Growing signal integrity issues in TSVs is one of
the major challenges of 3D integration. In this paper, different materials for the cores of the
vias and the interposers are investigated to find the best possible combination that can reduce
crosstalk and other losses like return loss and insertion loss in the TSVs. We have explored
glass and silicon as interposer materials. The simulation results indicate that glass is the best
option as interposer material although silicon interposer has some distinct advantages. For
via cores three materials - copper (Cu), tungsten (W) and Cu-W bimetal are considered. From
the analysis it can concluded that W would be better for high frequency applications due to
lower transmission coefficient. Cu offers higher conductivity, but it has larger thermal
expansion coefficient mismatch with silicon. The performance of Cu-W bimetal via would be
in between Cu and W. However, W has a thermal expansion coefficient close to silicon.
Therefore, bimetal Cu-W based TSV with W as the outer layer would be a suitable option for
high frequency 3D IC. Here, we performed the analysis in terms of return loss, transmission
coefficient and crosstalk in the vias.
Signal speed in current digital systems depends mainly on the delay of interconnects.
To overcome this delay problem and keep up with Moore’s law, 3D integrated circuit
(vertical integration of multiple dies) with through-silicon via (TSV) has been introduced to
ensure much smaller interconnect lengths, and lower delay and power consumption
compared to conventional 2D IC technology. Like 2D circuit, the estimation of 3D circuit
performance depends on different electrical parameters (capacitance, resistance, inductance)
of the TSV. So, accurate modeling of the electrical parameters of the TSV is essential for the
design and analysis of 3D ICs. We propose a set of new models to estimate the capacitance,
resistance, and inductance of a Cu-filled TSV. The proposed analytical models are derived
from the physical shape and the size of the TSV. The modeling approach is comprehensive
and includes both the cylindrical and tapered TSVs as well as the bumps.
On-chip integration of inductors has always been very challenging. However, for sub-
14nm on-chip applications, large area overhead imposed by the on-chip capacitors and
inductors has become a more severe concern. To overcome this issue and ensure power
integrity, a novel 3D Through-Silicon-Via (TSV) based inductor design is presented. The
proposed TSV based inductor has the potential to achieve both high density and high
performance. A new design of a Voltage Controlled Oscillator (VCO) utilizing the TSV
based inductor is also presented. The implementation of the VCO is intended to study the
feasibility, performance, and real-world application of the proposed TSV based inductor.Introduction -- Background of capacitance modeling of on-chip interconnect -- Accurate modeling of interconnect capacitance in multilevel interconnect structures for sub 22nm technology -- Analysis of different materials and structures for through silicon via and through glass via in 3D integrated circuits -- Impacts of different shapes of through-silicon-via core on 3D IC performance -- Accurate electrical modeling of cu-filled through-silicon-via (TSV) -- Design and characterize TSV based inductor for high frequency voltage-controlled oscillator design -- Conclusion and future wor
Novel fine pitch interconnection methods using metallised polymer spheres
There is an ongoing demand for electronics devices with more functionality while reducing size and cost, for example smart phones and tablet personal computers. This requirement has led to significantly higher integrated circuit input/output densities and therefore the need for off-chip interconnection pitch reduction. Flip-chip processes utilising anisotropic conductive adhesives anisotropic conductive films (ACAs/ACFs) have been successfully applied in liquid crystal display (LCD) interconnection for more than two decades. However the conflict between the need for a high particle density, to ensure sufficient the conductivity, without increasing the probability of short circuits has remained an issue since the initial utilization of ACAs/ACFs for interconnection. But this issue has become even more severe with the challenge of ultra-fine pitch interconnection.
This thesis advances a potential solution to this challenge where the conductive particles typically used in ACAs are selectively deposited onto the connections ensuring conductivity without bridging. The research presented in this thesis work has been undertaken to advance the fundamental understanding of the mechanical characteristics of micro-sized metal coated polymer particles (MCPs) and their application in fine or ultra-fine pitch interconnections. This included use of a new technique based on an in-situ nanomechanical system within SEM which was utilised to study MCP fracture and failure when undergoing deformation. Different loading conditions were applied to both uncoated polymer particles and MCPs, and the in-situ system enables their observation throughout compression. The results showed that both the polymer particles and MCP display viscoelastic characteristics with clear strain-rate hardening behaviour, and that the rate of compression therefore influences the initiation of cracks and their propagation direction.
Selective particle deposition using electrophoretic deposition (EPD) and magnetic deposition (MD) of Ni/Au-MCPs have been evaluated and a fine or ultra-fine pitch deposition has been demonstrated, followed by a subsequent assembly process. The MCPs were successfully positively charged using metal cations and this charging mechanism was analysed. A new theory has been proposed to explain the assembly mechanism of EPD of Ni/Au coated particles using this metal cation based charging method. The magnetic deposition experiments showed that sufficient magnetostatic interaction force between the magnetized particles and pads enables a highly selective dense deposition of particles. Successful bonding to form conductive interconnections with pre-deposited particles have been demonstrated using a thermocompression flip-chip bonder, which illustrates the applicable capability of EPD of MCPs for fine or ultra-fine pitch interconnection
El desafío económico japonés : Sus fundamentos y las consecuencias internacionales de su modelo de desarrollo económico social
Tesis doctoral Univ. Complutense de Madrid.ProQuestFac. de Ciencias Económicas y EmpresarialesTRUEpu