Title from PDF of title page viewed June 21, 2021Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 133-138)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2021To ensure maximum circuit reliability it is very important to estimate the circuit
performance and signal integrity in the circuit design phase. A full phase simulation for
performance estimation of a large-scale circuit not only require a massive computational
resource but also need a lot of time to produce acceptable results. The estimation of
performance/signal integrity of sub-nanometer circuits mostly depends on the interconnect
capacitance. So, an accurate model for interconnect capacitance can be used in the circuit
CAD (computer-aided design) tools for circuit performance estimation before circuit
fabrication which reduces the computational resource requirement as well as the time
constraints. We propose a new capacitance models for interconnect lines in multilevel
interconnect structures by geometrically modeling the electrical flux lines of the interconnect
lines. Closed-form equations have been derived analytically for ground and coupling
capacitance. First, the capacitance model for a single line is developed, and then the new
model is used to derive expressions for the capacitance of a line surrounded by neighboring
lines in the same and the adjacent layers above and below. These expressions are simple, and
the calculated results are within 10% of Ansys Q3D extracted values.
Through silicon via (TSV) is one of the key components of the emerging 3D ICs.
However, increasing number of TSVs in smaller silicon area leads to some severe negative
impacts on the performance of the 3D IC. Growing signal integrity issues in TSVs is one of
the major challenges of 3D integration. In this paper, different materials for the cores of the
vias and the interposers are investigated to find the best possible combination that can reduce
crosstalk and other losses like return loss and insertion loss in the TSVs. We have explored
glass and silicon as interposer materials. The simulation results indicate that glass is the best
option as interposer material although silicon interposer has some distinct advantages. For
via cores three materials - copper (Cu), tungsten (W) and Cu-W bimetal are considered. From
the analysis it can concluded that W would be better for high frequency applications due to
lower transmission coefficient. Cu offers higher conductivity, but it has larger thermal
expansion coefficient mismatch with silicon. The performance of Cu-W bimetal via would be
in between Cu and W. However, W has a thermal expansion coefficient close to silicon.
Therefore, bimetal Cu-W based TSV with W as the outer layer would be a suitable option for
high frequency 3D IC. Here, we performed the analysis in terms of return loss, transmission
coefficient and crosstalk in the vias.
Signal speed in current digital systems depends mainly on the delay of interconnects.
To overcome this delay problem and keep up with Moore’s law, 3D integrated circuit
(vertical integration of multiple dies) with through-silicon via (TSV) has been introduced to
ensure much smaller interconnect lengths, and lower delay and power consumption
compared to conventional 2D IC technology. Like 2D circuit, the estimation of 3D circuit
performance depends on different electrical parameters (capacitance, resistance, inductance)
of the TSV. So, accurate modeling of the electrical parameters of the TSV is essential for the
design and analysis of 3D ICs. We propose a set of new models to estimate the capacitance,
resistance, and inductance of a Cu-filled TSV. The proposed analytical models are derived
from the physical shape and the size of the TSV. The modeling approach is comprehensive
and includes both the cylindrical and tapered TSVs as well as the bumps.
On-chip integration of inductors has always been very challenging. However, for sub-
14nm on-chip applications, large area overhead imposed by the on-chip capacitors and
inductors has become a more severe concern. To overcome this issue and ensure power
integrity, a novel 3D Through-Silicon-Via (TSV) based inductor design is presented. The
proposed TSV based inductor has the potential to achieve both high density and high
performance. A new design of a Voltage Controlled Oscillator (VCO) utilizing the TSV
based inductor is also presented. The implementation of the VCO is intended to study the
feasibility, performance, and real-world application of the proposed TSV based inductor.Introduction -- Background of capacitance modeling of on-chip interconnect -- Accurate modeling of interconnect capacitance in multilevel interconnect structures for sub 22nm technology -- Analysis of different materials and structures for through silicon via and through glass via in 3D integrated circuits -- Impacts of different shapes of through-silicon-via core on 3D IC performance -- Accurate electrical modeling of cu-filled through-silicon-via (TSV) -- Design and characterize TSV based inductor for high frequency voltage-controlled oscillator design -- Conclusion and future wor
