Interconnect Planning for Physical Design of 3D Integrated Circuits

Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automation. This work addresses three selected, practically relevant design challenges: (i) increasing the constrained reusability of proven, reliable 2D intellectual property blocks, (ii) planning different types of (comparatively large) through-silicon vias with focus on their impact on design quality, as well as (iii) structural planning of massively-parallel, 3D-IC-specific interconnect structures during 3D floorplanning. A key concept of this work is to account for interconnect structures and their properties during early design phases in order to support effective and high-quality 3D-IC-design flows. To tackle the above listed challenges, modular design-flow extensions and methodologies have been developed. Experimental investigations reveal the effectiveness and efficiency of the proposed techniques, and provide findings on 3D integration with particular focus on interconnect structures. We suggest consideration of these findings when formulating guidelines for successful 3D-IC design automation.:1 Introduction 1.1 The 3D Integration Approach for Electronic Circuits 1.2 Technologies for 3D Integrated Circuits 1.3 Design Approaches for 3D Integrated Circuits 2 State of the Art in Design Automation for 3D Integrated Circuits 2.1 Thermal Management 2.2 Partitioning and Floorplanning 2.3 Placement and Routing 2.4 Power and Clock Delivery 2.5 Design Challenges 3 Research Objectives 4 Planning Through-Silicon Via Islands for Block-Level Design Reuse 4.1 Problems for Design Reuse in 3D Integrated Circuits 4.2 Connecting Blocks Using Through-Silicon Via Islands 4.2.1 Problem Formulation and Methodology Overview 4.2.2 Net Clustering 4.2.3 Insertion of Through-Silicon Via Islands 4.2.4 Deadspace Insertion and Redistribution 4.3 Experimental Investigation 4.3.1 Wirelength Estimation 4.3.2 Configuration 4.3.3 Results and Discussion 4.4 Summary and Conclusions 5 Planning Through-Silicon Vias for Design Optimization 5.1 Deadspace Requirements for Optimized Planning of Through-Silicon Vias 5.2 Multiobjective Design Optimization of 3D Integrated Circuits 5.2.1 Methodology Overview and Configuration 5.2.2 Techniques for Deadspace Optimization 5.2.3 Design-Quality Analysis 5.2.4 Planning Different Types of Through-Silicon Vias 5.3 Experimental Investigation 5.3.1 Configuration 5.3.2 Results and Discussion 5.4 Summary and Conclusions 6 3D Floorplanning for Structural Planning of Massive Interconnects 6.1 Block Alignment for Interconnects Planning in 3D Integrated Circuits 6.2 Corner Block List Extended for Block Alignment 6.2.1 Alignment Encoding 6.2.2 Layout Generation: Block Placement and Alignment 6.3 3D Floorplanning Methodology 6.3.1 Optimization Criteria and Phases and Related Cost Models 6.3.2 Fast Thermal Analysis 6.3.3 Layout Operations 6.3.4 Adaptive Optimization Schedule 6.4 Experimental Investigation 6.4.1 Configuration 6.4.2 Results and Discussion 6.5 Summary and Conclusions 7 Research Summary, Conclusions, and Outlook Dissertation Theses Notation Glossary BibliographyDreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück. In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase. Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich.:1 Introduction 1.1 The 3D Integration Approach for Electronic Circuits 1.2 Technologies for 3D Integrated Circuits 1.3 Design Approaches for 3D Integrated Circuits 2 State of the Art in Design Automation for 3D Integrated Circuits 2.1 Thermal Management 2.2 Partitioning and Floorplanning 2.3 Placement and Routing 2.4 Power and Clock Delivery 2.5 Design Challenges 3 Research Objectives 4 Planning Through-Silicon Via Islands for Block-Level Design Reuse 4.1 Problems for Design Reuse in 3D Integrated Circuits 4.2 Connecting Blocks Using Through-Silicon Via Islands 4.2.1 Problem Formulation and Methodology Overview 4.2.2 Net Clustering 4.2.3 Insertion of Through-Silicon Via Islands 4.2.4 Deadspace Insertion and Redistribution 4.3 Experimental Investigation 4.3.1 Wirelength Estimation 4.3.2 Configuration 4.3.3 Results and Discussion 4.4 Summary and Conclusions 5 Planning Through-Silicon Vias for Design Optimization 5.1 Deadspace Requirements for Optimized Planning of Through-Silicon Vias 5.2 Multiobjective Design Optimization of 3D Integrated Circuits 5.2.1 Methodology Overview and Configuration 5.2.2 Techniques for Deadspace Optimization 5.2.3 Design-Quality Analysis 5.2.4 Planning Different Types of Through-Silicon Vias 5.3 Experimental Investigation 5.3.1 Configuration 5.3.2 Results and Discussion 5.4 Summary and Conclusions 6 3D Floorplanning for Structural Planning of Massive Interconnects 6.1 Block Alignment for Interconnects Planning in 3D Integrated Circuits 6.2 Corner Block List Extended for Block Alignment 6.2.1 Alignment Encoding 6.2.2 Layout Generation: Block Placement and Alignment 6.3 3D Floorplanning Methodology 6.3.1 Optimization Criteria and Phases and Related Cost Models 6.3.2 Fast Thermal Analysis 6.3.3 Layout Operations 6.3.4 Adaptive Optimization Schedule 6.4 Experimental Investigation 6.4.1 Configuration 6.4.2 Results and Discussion 6.5 Summary and Conclusions 7 Research Summary, Conclusions, and Outlook Dissertation Theses Notation Glossary Bibliograph

Heurísticas bioinspiradas para el problema de Floorplanning 3D térmico de dispositivos MPSoCs

Tesis inédita de la Universidad Complutense de Madrid, Facultad de Informática, Departamento de Arquitectura de Computadores y Automática, leída el 20-06-2013Depto. de Arquitectura de Computadores y AutomáticaFac. de InformáticaTRUEunpu

Algorithmic techniques for physical design : macro placement and under-the-cell routing

With the increase of chip component density and new manufacturability constraints imposed by modern technology nodes, the role of algorithms for electronic design automation is key to the successful implementation of integrated circuits. Two of the critical steps in the physical design flows are macro placement and ensuring all design rules are honored after timing closure. This thesis proposes contributions to help in these stages, easing time-consuming manual steps and helping physical design engineers to obtain better layouts in reduced turnaround time. The first contribution is under-the-cell routing, a proposal to systematically connect standard cell components via lateral pins in the lower metal layers. The aim is to reduce congestion in the upper metal layers caused by extra metal and vias, decreasing the number of design rule violations. To allow cells to connect by abutment, a standard cell library is enriched with instances containing lateral pins in a pre-selected sharing track. Algorithms are proposed to maximize the numbers of connections via lateral connection by mapping placed cell instances to layouts with lateral pins, and proposing local placement modifications to increase the opportunities for such connections. Experimental results show a significant decrease in the number of pins, vias, and in number of design rule violations, with negligible impact on wirelength and timing. The second contribution, done in collaboration with eSilicon (a leading ASIC design company), is the creation of HiDaP, a macro placement tool for modern industrial designs. The proposed approach follows a multilevel scheme to floorplan hierarchical blocks, composed of macros and standard cells. By exploiting RTL information available in the netlist, the dataflow affinity between these blocks is modeled and minimized to find a macro placement with good wirelength and timing properties. The approach is further extended to allow additional engineer input, such as preferred macro locations, and also spectral and force methods to guide the floorplanning search. Experimental results show that the layouts generated by HiDaP outperforms those obtained by a state-of-the-art EDA physical design software, with similar wirelength and better timing when compared to manually designed tape-out ready macro placements. Layouts obtained by HiDaP have successfully been brought to near timing closure with one to two rounds of small modifications by physical design engineers. HiDaP has been fully integrated in the design flows of the company and its development remains an ongoing effort.A causa de l'increment de la densitat de components en els xip i les noves restriccions de disseny imposades pels últims nodes de fabricació, el rol de l'algorísmia en l'automatització del disseny electrònic ha esdevingut clau per poder implementar circuits integrats. Dos dels passos crucials en el procés de disseny físic és el placement de macros i assegurar la correcció de les regles de disseny un cop les restriccions de timing del circuit són satisfetes. Aquesta tesi proposa contribucions per ajudar en aquests dos reptes, facilitant laboriosos passos manuals en el procés i ajudant als enginyers de disseny físic a obtenir millors resultats en menys temps. La primera contribució és el routing "under-the-cell", una proposta per connectar cel·les estàndard usant pins laterals en les capes de metall inferior de manera sistemàtica. L'objectiu és reduir la congestió en les capes de metall superior causades per l'ús de metall i vies, i així disminuir el nombre de violacions de regles de disseny. Per permetre la connexió lateral de cel·les, estenem una llibreria de cel·les estàndard amb dissenys que incorporen connexions laterals. També proposem modificacions locals al placement per permetre explotar aquest tipus de connexions més sovint. Els resultats experimentals mostren una reducció significativa en el nombre de pins, vies i nombre de violacions de regles de disseny, amb un impacte negligible en wirelength i timing. La segona contribució, desenvolupada en col·laboració amb eSilicon (una empresa capdavantera en disseny ASIC), és el desenvolupament de HiDaP, una eina de macro placement per a dissenys industrials actuals. La proposta segueix un procés multinivell per fer el floorplan de blocks jeràrquics, formats per macros i cel·les estàndard. Mitjançant la informació RTL disponible en la netlist, l'afinitat de dataflow entre els mòduls es modela i minimitza per trobar macro placements amb bones propietats de wirelength i timing. La proposta també incorpora la possibilitat de rebre input addicional de l'enginyer, com ara suggeriments de les posicions de les macros. Finalment, també usa mètodes espectrals i de forçes per guiar la cerca de floorplans. Els resultats experimentals mostren que els dissenys generats amb HiDaP són millors que els obtinguts per eines comercials capdavanteres de EDA. Els resultats també mostren que els dissenys presentats poden obtenir un wirelength similar i millor timing que macro placements obtinguts manualment, usats per fabricació. Alguns dissenys obtinguts per HiDaP s'han dut fins a timing-closure en una o dues rondes de modificacions incrementals per part d'enginyers de disseny físic. L'eina s'ha integrat en el procés de disseny de eSilicon i el seu desenvolupament continua més enllà de les aportacions a aquesta tesi

Algorithmic techniques for physical design : macro placement and under-the-cell routing

With the increase of chip component density and new manufacturability constraints imposed by modern technology nodes, the role of algorithms for electronic design automation is key to the successful implementation of integrated circuits. Two of the critical steps in the physical design flows are macro placement and ensuring all design rules are honored after timing closure. This thesis proposes contributions to help in these stages, easing time-consuming manual steps and helping physical design engineers to obtain better layouts in reduced turnaround time. The first contribution is under-the-cell routing, a proposal to systematically connect standard cell components via lateral pins in the lower metal layers. The aim is to reduce congestion in the upper metal layers caused by extra metal and vias, decreasing the number of design rule violations. To allow cells to connect by abutment, a standard cell library is enriched with instances containing lateral pins in a pre-selected sharing track. Algorithms are proposed to maximize the numbers of connections via lateral connection by mapping placed cell instances to layouts with lateral pins, and proposing local placement modifications to increase the opportunities for such connections. Experimental results show a significant decrease in the number of pins, vias, and in number of design rule violations, with negligible impact on wirelength and timing. The second contribution, done in collaboration with eSilicon (a leading ASIC design company), is the creation of HiDaP, a macro placement tool for modern industrial designs. The proposed approach follows a multilevel scheme to floorplan hierarchical blocks, composed of macros and standard cells. By exploiting RTL information available in the netlist, the dataflow affinity between these blocks is modeled and minimized to find a macro placement with good wirelength and timing properties. The approach is further extended to allow additional engineer input, such as preferred macro locations, and also spectral and force methods to guide the floorplanning search. Experimental results show that the layouts generated by HiDaP outperforms those obtained by a state-of-the-art EDA physical design software, with similar wirelength and better timing when compared to manually designed tape-out ready macro placements. Layouts obtained by HiDaP have successfully been brought to near timing closure with one to two rounds of small modifications by physical design engineers. HiDaP has been fully integrated in the design flows of the company and its development remains an ongoing effort.A causa de l'increment de la densitat de components en els xip i les noves restriccions de disseny imposades pels últims nodes de fabricació, el rol de l'algorísmia en l'automatització del disseny electrònic ha esdevingut clau per poder implementar circuits integrats. Dos dels passos crucials en el procés de disseny físic és el placement de macros i assegurar la correcció de les regles de disseny un cop les restriccions de timing del circuit són satisfetes. Aquesta tesi proposa contribucions per ajudar en aquests dos reptes, facilitant laboriosos passos manuals en el procés i ajudant als enginyers de disseny físic a obtenir millors resultats en menys temps. La primera contribució és el routing "under-the-cell", una proposta per connectar cel·les estàndard usant pins laterals en les capes de metall inferior de manera sistemàtica. L'objectiu és reduir la congestió en les capes de metall superior causades per l'ús de metall i vies, i així disminuir el nombre de violacions de regles de disseny. Per permetre la connexió lateral de cel·les, estenem una llibreria de cel·les estàndard amb dissenys que incorporen connexions laterals. També proposem modificacions locals al placement per permetre explotar aquest tipus de connexions més sovint. Els resultats experimentals mostren una reducció significativa en el nombre de pins, vies i nombre de violacions de regles de disseny, amb un impacte negligible en wirelength i timing. La segona contribució, desenvolupada en col·laboració amb eSilicon (una empresa capdavantera en disseny ASIC), és el desenvolupament de HiDaP, una eina de macro placement per a dissenys industrials actuals. La proposta segueix un procés multinivell per fer el floorplan de blocks jeràrquics, formats per macros i cel·les estàndard. Mitjançant la informació RTL disponible en la netlist, l'afinitat de dataflow entre els mòduls es modela i minimitza per trobar macro placements amb bones propietats de wirelength i timing. La proposta també incorpora la possibilitat de rebre input addicional de l'enginyer, com ara suggeriments de les posicions de les macros. Finalment, també usa mètodes espectrals i de forçes per guiar la cerca de floorplans. Els resultats experimentals mostren que els dissenys generats amb HiDaP són millors que els obtinguts per eines comercials capdavanteres de EDA. Els resultats també mostren que els dissenys presentats poden obtenir un wirelength similar i millor timing que macro placements obtinguts manualment, usats per fabricació. Alguns dissenys obtinguts per HiDaP s'han dut fins a timing-closure en una o dues rondes de modificacions incrementals per part d'enginyers de disseny físic. L'eina s'ha integrat en el procés de disseny de eSilicon i el seu desenvolupament continua més enllà de les aportacions a aquesta tesi.Postprint (published version

On the construction of rectilinear Steiner minimum trees among obstacles.

Rectilinear Steiner minimum tree (RSMT) problem asks for a shortest tree spanning a set of given terminals using only horizontal and vertical lines. Construction of RSMTs is an important problem in VLSI physical design. It is useful for both the detailed and global routing steps, and it is important for congestion, wire length and timing estimations during the floorplanning or placement step. The original RSMT problem assumes no obstacle in the routing region. However, in today’s designs, there can be many routing blockages, like macro cells, IP blocks and pre-routed nets. Therefore, the RSMT problem with blockages has become an important problem in practice and has received a lot of research attentions in the recent years. The RSMT problem has been shown to be NP-complete, and the introduction of obstacles has made this problem even more complicated.In the first part of this thesis, we propose an exact algorithm, called ObSteiner, for the construction of obstacle-avoiding RSMT (OARSMT) in the presence of complex rectilinear obstacles. Our work is developed based on the GeoSteiner approach in which full Steiner trees (FSTs) are first constructed and then combined into a RSMT. We modify and extend the algorithm to allow rectilinear obstacles in the routing region. We prove that by adding virtual terminals to each routing obstacle, the FSTs in the presence of obstacles will follow some very simple structures. A two-phase approach is then developed for the construction of OARSMTs. In the first phase, we generate a set of FSTs. In the second phase, the FSTs generated in the first phase are used to construct an OARSMT. Experimental results show that ObSteiner is able to handle problems with hundreds of terminals in the presence of up to two thousand obstacles, generating an optimal solution in a reasonable amount of time.In the second part of this thesis, we propose the OARSMT problem with slew constraints over obstacles. In modern VLSI designs, obstacles usually block a fraction of metal layers only making it possible to route over the obstacles. However, since buffers cannot be place on top of any obstacle, we should avoid routing long wires over obstacles. Therefore, we impose the slew constraints for the interconnects that are routed over obstacles. To deal with this problem, we analyze the optimal solutions and prove that the internal trees with signal direction over an obstacle will follow some simple structures. Based on this observation, we propose an exact algorithm, called ObSteiner with slew constraints, that is able to find an optimal solution in the extended Hanan grid. Experimental results show that the proposed algorithm is able to reduce nearly 5% routing resources on average in comparison with the OARSMT algorithm and is also very much faster.Huang, Tao.Thesis (Ph.D.)--Chinese University of Hong Kong, 2013.Includes bibliographical references (leaves [137]-144).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- The rectilinear Steiner minimum tree problem --- p.1Chapter 1.2 --- Applications --- p.3Chapter 1.3 --- Obstacle consideration --- p.5Chapter 1.4 --- Thesis outline --- p.6Chapter 1.5 --- Thesis contributions --- p.8Chapter 2 --- Background --- p.11Chapter 2.1 --- RSMT algorithms --- p.11Chapter 2.1.1 --- Heuristics --- p.11Chapter 2.1.2 --- Exact algorithms --- p.20Chapter 2.2 --- OARSMT algorithms --- p.30Chapter 2.2.1 --- Heuristics --- p.30Chapter 2.2.2 --- Exact algorithms --- p.33Chapter 3 --- ObSteiner - an exact OARSMT algorithm --- p.37Chapter 3.1 --- Introduction --- p.38Chapter 3.2 --- Preliminaries --- p.39Chapter 3.2.1 --- OARSMT problem formulation --- p.39Chapter 3.2.2 --- An exact RSMT algorithm --- p.40Chapter 3.3 --- OARSMT decomposition --- p.42Chapter 3.3.1 --- Full Steiner trees among complex obstacles --- p.42Chapter 3.3.2 --- More Theoretical results --- p.59Chapter 3.4 --- OARSMT construction --- p.62Chapter 3.4.1 --- FST generation --- p.62Chapter 3.4.2 --- Pruning of FSTs --- p.66Chapter 3.4.3 --- FST concatenation --- p.71Chapter 3.5 --- Incremental construction --- p.82Chapter 3.6 --- Experiments --- p.83Chapter 4 --- ObSteiner with slew constraints --- p.97Chapter 4.1 --- Introduction --- p.97Chapter 4.2 --- Problem Formulation --- p.100Chapter 4.3 --- Overview of our approach --- p.103Chapter 4.4 --- Internal tree structures in an optimal solution --- p.103Chapter 4.5 --- Algorithm --- p.126Chapter 4.5.1 --- EFST and SCIFST generation --- p.127Chapter 4.5.2 --- Concatenation --- p.129Chapter 4.5.3 --- Incremental construction --- p.131Chapter 4.6 --- Experiments --- p.131Chapter 5 --- Conclusion --- p.135Bibliography --- p.13

High performance algorithms for large scale placement problem

Placement is one of the most important problems in electronic design automation (EDA). An inferior placement solution will not only affect the chip’s performance but might also make it nonmanufacturable by producing excessive wirelength, which is beyond available routing resources. Although placement has been extensively investigated for several decades, it is still a very challenging problem mainly due to that design scale has been dramatically increased by order of magnitudes and the increasing trend seems unstoppable. In modern design, chips commonly integrate millions of gates that require over tens of metal routing layers. Besides, new manufacturing techniques bring out new requests leading to that multi-objectives should be optimized simultaneously during placement. Our research provides high performance algorithms for placement problem. We propose (i) a high performance global placement core engine POLAR; (ii) an efficient routability-driven placer POLAR 2.0, which is an extension of POLAR to deal with routing congestion; (iii) an ultrafast global placer POLAR 3.0, which explore parallelism on POLAR and can make full use of multi-core system; (iv) some efficient triple patterning lithography (TPL) aware detailed placement algorithms

Thermal designs, models and optimization for three-dimensional integrated circuits

Three-dimensional integrated circuits (3D ICs), a novel packaging technology, are heavily studied to enable improved performance with denser packaging and reduced interconnects. Despite numerous advantages, thermal management is the biggest bottleneck to expanding the applications of this device stacking technology. In addition to implementing the thermal-aware designs of existing methodologies, it is necessary to implement new features to dissipate heat efficiently. This work presents two main aspects of thermal designs: on-chip level and package level. First, we propose a novel thermal-aware physical design on chip between devices. We aim to mitigate localized hotspots to ensure the functionality by adding thermal fin geometry to existing thermal through- silicon via (TTSV). We analyze design requirements of thermal fin for single TTSV as well as TTSV cluster designs with the goal of maximizing heat dissipation while minimizing the interference with routing and area consumption. An analytical model of the three-dimensional system and thermal resistance circuit is built for accurate and runtime-efficient thermal analysis. In terms of high-performance computing systems in 3D ICs, thermal bottle- necks are much more challenging with merely on-chip design solutions. Inter- tier liquid cooling microchannel layers have been introduced into 3D ICs as an integrated cooling mechanism to tackle the thermal degradation. Many existing research works optimize microchannel designs based on runtime-intensive numerical methods or inaccurate thermo-fluid models. Hence, we propose an accurate but compact closed-form model of tapered microchannel to capture the relationship between the channel geometry and heat transfer performance. To improve the accuracy, our correlations are based on the developing flow model and derived from numerical simulation data on a sub- set of multiple channel parameters. Our model achieves 57% less error in Nusselt number and 45 % less error in pressure drop for channels with inlet width 100-400 μm compared to a commonly used approximate model on fully developed flow. Next, we present the correlations for diverging channels as well as complete correlations that extend to any linearly tapering channel models, that include diverging shape, uniformly rectangular shape and converging shape. The complete models provide the flexibility to analyze and optimize any arbitrary geometry based on the piecewise linear channel wall assumption. Finally, we demonstrate the optimized channel designs using the derived correlations. Tapered channel models provided the flexibility to incorporate any arbitrary shapes and explore the advanced geometries during the optimization. The microchannel is divided into small segments in axial direction from inlet to outlet and piecewise optimized. The simulated annealing method is applied in our optimization, and channel width at one randomly chosen segment interface is altered to evaluate the design at each iteration. The objective is to minimize the overall thermal resistance while pressure drop is maintained less than a threshold value and channel widths have minimum and maximum boundaries. We compare the designs with the optimization based on fully developed flow models and verify the channel performance through numerical simulations. To guarantee optimality, accurate analysis is crucial. Our proposed models have significantly improved the accuracy by applying the appropriate flow assumption. However, many opportunities exist to increase the design flexibility and the accuracy. Fluid conditions, such as coolant material and varying volumetric flow rate, can also be part of the optimization parameters to expand the design scope. Moreover, physical phenomena, such as reduced friction on the channel walls or a vortex created on abrupt angle changes, can be considered to improve the accuracy in the closed-form models

Drawing graphs for cartographic applications

Graph Drawing is a relatively young area that combines elements of graph theory, algorithms, (computational) geometry and (computational) topology. Research in this field concentrates on developing algorithms for drawing graphs while satisfying certain aesthetic criteria. These criteria are often expressed in properties like edge complexity, number of edge crossings, angular resolutions, shapes of faces or graph symmetries and in general aim at creating a drawing of a graph that conveys the information to the reader in the best possible way. Graph drawing has applications in a wide variety of areas which include cartography, VLSI design and information visualization. In this thesis we consider several graph drawing problems. The first problem we address is rectilinear cartogram construction. A cartogram, also known as value-by-area map, is a technique used by cartographers to visualize statistical data over a set of geographical regions like countries, states or counties. The regions of a cartogram are deformed such that the area of a region corresponds to a particular geographic variable. The shapes of the regions depend on the type of cartogram. We consider rectilinear cartograms of constant complexity, that is cartograms where each region is a rectilinear polygon with a constant number of vertices. Whether a cartogram is good is determined by how closely the cartogram resembles the original map and how precisely the area of its regions describe the associated values. The cartographic error is defined for each region as jAc¡Asj=As, where Ac is the area of the region in the cartogram and As is the specified area of that region, given by the geographic variable to be shown. In this thesis we consider the construction of rectilinear cartograms that have correct adjacencies of the regions and zero cartographic error. We show that any plane triangulated graph admits a rectilinear cartogram where every region has at most 40 vertices which can be constructed in O(nlogn) time. We also present experimental results that show that in practice the algorithm works significantly better than suggested by the complexity bounds. In our experiments on real-world data we were always able to construct a cartogram where the average number of vertices per region does not exceed five. Since a rectangle has four vertices, this means that most of the regions of our rectilinear car tograms are in fact rectangles. Moreover, the maximum number vertices of each region in these cartograms never exceeded ten. The second problem we address in this thesis concerns cased drawings of graphs. The vertices of a drawing are commonly marked with a disk, but differentiating between vertices and edge crossings in a dense graph can still be difficult. Edge casing is a wellknown method—used, for example, in electrical drawings, when depicting knots, and, more generally, in information visualization—to alleviate this problem and to improve the readability of a drawing. A cased drawing orders the edges of each crossing and interrupts the lower edge in an appropriate neighborhood of the crossing. One can also envision that every edge is encased in a strip of the background color and that the casing of the upper edge covers the lower edge at the crossing. If there are no application-specific restrictions that dictate the order of the edges at each crossing, then we can in principle choose freely how to arrange them. However, certain orders will lead to a more readable drawing than others. In this thesis we formulate aesthetic criteria for a cased drawing as optimization problems and solve these problems. For most of the problems we present either a polynomial time algorithm or demonstrate that the problem is NP-hard. Finally we consider a combinatorial question in computational topology concerning three types of objects: closed curves in the plane, surfaces immersed in the plane, and surfaces embedded in space. In particular, we study casings of closed curves in the plane to decide whether these curves can be embedded as the boundaries of certain special surfaces. We show that it is NP-complete to determine whether an immersed disk is the projection of a surface embedded in space, or whether a curve is the boundary of an immersed surface in the plane that is not constrained to be a disk. However, when a casing is supplied with a self-intersecting curve, describing which component of the curve lies above and which below at each crossing, we can determine in time linear in the number of crossings whether the cased curve forms the projected boundary of a surface in space. As a related result, we show that an immersed surface with a single boundary curve that crosses itself n times has at most 2n=2 combinatorially distinct spatial embeddings and we discuss the existence of fixed-parameter tractable algorithms for related problems

Doctor of Philosophy

dissertationRecent breakthroughs in silicon photonics technology are enabling the integration of optical devices into silicon-based semiconductor processes. Photonics technology enables high-speed, high-bandwidth, and high-fidelity communications on the chip-scale-an important development in an increasingly communications-oriented semiconductor world. Significant developments in silicon photonic manufacturing and integration are also enabling investigations into applications beyond that of traditional telecom: sensing, filtering, signal processing, quantum technology-and even optical computing. In effect, we are now seeing a convergence of communications and computation, where the traditional roles of optics and microelectronics are becoming blurred. As the applications for opto-electronic integrated circuits (OEICs) are developed, and manufacturing capabilities expand, design support is necessary to fully exploit the potential of this optics technology. Such design support for moving beyond custom-design to automated synthesis and optimization is not well developed. Scalability requires abstractions, which in turn enables and requires the use of optimization algorithms and design methodology flows. Design automation represents an opportunity to take OEIC design to a larger scale, facilitating design-space exploration, and laying the foundation for current and future optical applications-thus fully realizing the potential of this technology. This dissertation proposes design automation for integrated optic system design. Using a buildingblock model for optical devices, we provide an EDA-inspired design flow and methodologies for optical design automation. Underlying these flows and methodologies are new supporting techniques in behavioral and physical synthesis, as well as device-resynthesis techniques for thermal-aware system integration. We also provide modeling for optical devices and determine optimization and constraint parameters that guide the automation techniques. Our techniques and methodologies are then applied to the design and optimization of optical circuits and devices. Experimental results are analyzed to evaluate their efficacy. We conclude with discussions on the contributions and limitations of the approaches in the context of optical design automation, and describe the tremendous opportunities for future research in design automation for integrated optics

Transistor-Level Layout of Integrated Circuits

In this dissertation, we present the toolchain BonnCell and its underlying algorithms. It has been developed in close cooperation with the IBM Corporation and automatically generates the geometry for functional groups of 2 to approximately 50 transistors. Its input consists of a set of transistors, including properties like their sizes and their types, a specification of their connectivity, and parameters to flexibly control the technological framework as well as the algorithms' behavior. Using this data, the tool computes a detailed geometric realization of the circuit as polygonal shapes on 16 layers. To this end, a placement routine configures the transistors and arranges them in the plane, which is the main subject of this thesis. Subsequently, a routing engine determines wires connecting the transistors to ensure the circuit's desired functionality. We propose and analyze a family of algorithms that arranges sets of transistors in the plane such that a multi-criteria target function is optimized. The primary goal is to obtain solutions that are as compact as possible because chip area is a valuable resource in modern techologies. In addition to the core algorithms we formulate variants that handle particularly structured instances in a suitable way. We will show that for 90% of the instances in a representative test bed provided by IBM, BonnCell succeeds to generate fully functional layouts including the placement of the transistors and a routing of their interconnections. Moreover, BonnCell is in wide use within IBM's groups that are concerned with transistor-level layout - a task that has been performed manually before our automation was available. Beyond the processing of isolated test cases, two large-scale examples for applications of the tool in the industry will be presented: On the one hand the initial design phase of a large SRAM unit required only half of the expected 3 month period, on the other hand BonnCell could provide valuable input aiding central decisions in the early concept phase of the new 14 nm technology generation