Realization of a single-chip, SiGe:C-based power amplifier for multi-band WiMAX applications

A fully-integrated Multi-Band PA using 0.25 μm SiGe:C process with an output power of above 25 dBm is presented. The behaviour of the amplifier has been optimized for multi-band operation covering, 2.4 GHz, 3.6 GHz and 5.4 GHz (UWB-WiMAX) frequency bands for higher 1-dB compression point and efficiency. Multi-band operation is achieved using multi-stage topology. Parasitic components of active devices are also used as matching components, in turn decreasing the number of matching component. Measurement results of the PA provided the following performance parameters: 1-dB compression point of 20.5 dBm, gain value of 23 dB and efficiency value of %7 operation for the 2.4 GHz band; 1-dB compression point of 25.5 dBm, gain value of 31.5 dB and efficiency value of %17.5 for the 3.6 GHz band; 1-dB compression point of 22.4 dBm, gain value of 24.4 dB and efficiency value of %9.5 for the 5.4 GHz band. Measurement results show that using multi-stage topologies and implementing each parasitic as part of the matching network component has provided a wider-band operation with higher output power levels, above 25 dBm, with SiGe:C process

Analysis and Measurement Technique for 1- dB Compression Point of Single Balanced RF Mixer

The present paper discusses the basic working and operation of RF Mixers being used broadly for communication purposes. In the present paper we have discussed various important parameters of Mixer and elaborately described the instrument setup and measurement techniques for measuring the most vital parameter for analyzing performance of mixer i.e., 1-dB Compression Point (P1dB). 1- dB compression point is very significant parameter as it indicates the power level that causes the gain to drop by 1 dB from its small signal value. In this paper we have described test set up for measuring this important parameter with various measuring instruments and has obtained good agreement between the predictions and experimental data. Index Terms- Single diode mixers, 1 dB Compression Point (P1dB), Down Converter, VM-3 Receiver, Power meter, Attenuato

A 60 GHz CMOS Power Amplifier for Wireless Communications

This paper presents a 60 GHz power amplifier (PA) suitable for wireless communications. The two-stage wideband PA is fabricated in 55 nm CMOS. Measurement results show that the PA obtains a peak gain of 16 dB over a -3 dB bandwidth from 57 GHz to 67 GHz. It archives an output 1 dB compression point (OP1dB) of 4 dbm and a peak power added efficiency (PAE) of 12.6%. The PA consumes a total DC power of 38.3 mW from a 1.2 V supply voltage while its core occupies a chip area of 0.45 mm2

Low-Power D-Band CMOS Amplifier for Ultrahigh-Speed Wireless Communications

This paper presents a low-power D-Band amplifier suitable for ultrahigh-speed wireless communications. The three-stage fully differential amplifier with capacitive neutralization is fabricated in 40 nm CMOS provided by TSMC. Measurement results show that the D-band amplifier obtains a peak gain of 9.6 dB over a -3 dB bandwidth from 138 GHz to 164.5 GHz. It exhibits an output 1 dB compression point (OP1dB) of 1.5 dbm at the center frequency of 150 GHz. The amplifier consumes a low power of 27.3 mW from a 0.7 V supply voltage while its core occupies a chip area of 0.06 mm2

A 50 GHz SiGe BiCMOS active bandpass filter

Abstract: This paper presents a second-order active bandpass filter (BPF) at millimeter-wave frequency band using 0.13 μm SiGe BiCMOS technology. A complementary cross-coupled pair based negative resistance technique is applied to compensate for the resistive losses of microstrip line resonators. The proposed active BPF is simulated using the Keysight Technologies (formerly Agilent’s Electronic Measurement Group) Advanced Design System 2016.01. The center frequency (fc), 3-dB bandwidth, and fractional bandwidth of the simulated BPF are 53.85 GHz, 14.18 GHz, and 26.33%, respectively. The BPF shows an insertion loss (IL) of 0.33 dB and a return loss (RL) of 18.03 dB at fc. The minimum IL of 0.10 dB and best RL of 26.03 dB are observed in the passband. The noise figure and input 1-dB compression point (PldB) at fc are 7.93 dB and -3.67 dBm, respectively. The power dissipation is 2.62 mW at 1.6 V supply voltage. For the input power level of -10 dBm, the power level of the second harmonic is -46.02 dBc

Design Of Power Amplifier For Ultra-Wideband (UWB) Applications Using Silterra 0.18 μm Cmos Technology

A power amplifier for Ultra-Wideband (UWB) transceiver system is presented. UWB is a high data rates (up to 480 Mbps) wireless communication technology for short distance (less than 10m) applications. UWB technology is a low power (-41.3 dBm/MHz) wireless communications that can coexist with the existing technology such as Bluetooth, GPS (Global Positioning System) and WiFi. The power amplifier is designed for UWB direct conversion (DICON) transceiver system that employs Multi-band Orthogonal Frequency Division Multiplexing (MB-OFDM) approach and operates in mode 1 (3.1 to 4.9GHz) of UWB spectrum. The power amplifier is designed using Silterra 0.18μm CMOS technology in three different version which consists of IDEAL, SIL18RF and ASITIC case. The power amplifier has been implemented in two versions which are SIL18RF inductor and ASITIC inductor. IDEAL case achieved S11 < -31 dB, S12 < -75 dB, S21 = 19.45 ± 0.64 dB and S22 < -10 dB. IDEAL version also achieved input referred 1 dB compression point of -17.44 dBm and maximum output power of 1.49 dBm while consuming only 31.3 mW. On the other hand, SIL18RF version achieved S11 < -10 dB, S12 < -82 dB, S21 = 16.39 ± 0.68 dB and S22 < -10.3 dB while ASITIC version achieved S11 < -25 dB, S12 < -82 dB, S21 = 19.66 ± 1.45 dB and S22 < -10.8 dB. SIL18RF version obtained input referred 1 dB compression point of -14.4 dBm and maximum output power of 1.38 dBm while ASITIC version achieved input referred 1 dB compression point of -13.57 dBm and maximum output power of 2.12 dBm. SIL18RF and ASITIC version only consume 30.87 mW and 31.63mW respectively. The layout dimension of SIL18RF version is 3.7mm x 2.6mm which is bigger than ASITIC version estimated to be 0.55mm x 0.85mm. A PCB (Printed Circuit Board) with dimension of 60mm x 80mm has been designed to characterize SIL18RF fabricated chip. Beside power amplifier design, a measurement task has been carried out to evaluate the performance of MAX2242EVKIT using radio frequency high end tools. From measurement results, MAX2242 can produce +26 dBm output power at 5 dBm input power and 3.3V power supply

A 900 MHz, 0.9 V low-power CMOS downconversion mixer

A low-voltage, low-power mixer operating at a supply voltage of 0.9 V while consuming 4.7 mW is presented. The circuit achieves the multiplication using current mode processing. Moreover, non-conventional differential pairs that do not require current tail generators are utilized. The circuit has been fabricated in a standard double-poly, triple-metal 0.35 /spl mu/m CMOS process having a threshold voltage of 0.6 V. Measurement results for 900 MHz and 800 MHz input signals indicate that the circuit has an IIP3 of 3.5 dBm, a 1 dB compression point of -8 dBm and a noise figure of 13.5 dB.peer-reviewe

A low voltage 900 MHz CMOS mixer.

by Cheng Wang Chi.Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.Includes bibliographical references (leaves 108-111).Abstracts in English and Chinese.Abstract --- p.i摘要 --- p.iiiAcknowledgments --- p.vContents --- p.viiList of Tables --- p.xiiiList of Figures --- p.xivChapter Chapter1 --- Introduction --- p.1Chapter 1.1 --- Motivation --- p.1Chapter 1.2 --- Technical Challenges of CMOS RF Design --- p.2Chapter 1.3 --- General Background --- p.2Chapter 1.3.1 --- Bipolar and CMOS Mixers --- p.4Chapter 1.4 --- Research Goal --- p.4Chapter 1.5 --- Thesis Outline --- p.5Chapter Chapter2 --- RF Fundamentals --- p.6Chapter 2.1 --- Introduction --- p.6Chapter 2.2 --- Frequency Translation --- p.6Chapter 2.3 --- Conversion Gain --- p.8Chapter 2.4 --- Linearity --- p.8Chapter 2.4.1 --- 1-dB Compression Point --- p.11Chapter 2.4.2 --- Third Intercept Point (IP3) --- p.11Chapter 2.5 --- Dynamic Range (DR) --- p.13Chapter 2.5.1 --- Spurious-Free Dynamic Range (SFDR) --- p.13Chapter 2.5.2 --- Blocking Dynamic Range (BDR) --- p.14Chapter 2.6 --- Blocking and Desensitization --- p.15Chapter 2.7 --- Port-to-Port Isolation --- p.15Chapter 2.8 --- Single-Balanced and Double-Balanced Mixers --- p.16Chapter 2.9 --- Noise --- p.16Chapter 2.9.1 --- Noise in the Local Oscillator --- p.17Chapter 2.9.2 --- Noise Figure --- p.18Chapter Chapter3 --- Downconversion Mixer --- p.19Chapter 3.1 --- Introduction --- p.19Chapter 3.2 --- Review of Mixer Topology --- p.19Chapter 3.2.1 --- Square-Law Mixer --- p.20Chapter 3.2.2 --- CMOS Gilbert Cell --- p.21Chapter 3.2.3 --- Potentiometric Mixer --- p.22Chapter 3.2.4 --- Subsampling Mixer --- p.23Chapter Chapter4 --- Proposed Downconversion Mixer --- p.24Chapter 4.1 --- Analysis of Proposal Mixer --- p.24Chapter 4.2 --- Current Folded Mirror Mixer --- p.24Chapter 4.2.1 --- Operating Principle --- p.25Chapter 4.2.2 --- Large Signal Analysis --- p.26Chapter 4.2.3 --- Small Signal Analysis --- p.29Chapter 4.3 --- Current Mode Mixer --- p.32Chapter 4.3.1 --- Operating Principle --- p.33Chapter 4.3.2 --- Large Signal Analysis --- p.33Chapter 4.3.3 --- Small Signal Analysis --- p.34Chapter 4.3.4 --- V-I Converter --- p.36Chapter 4.3.4.1 --- Equation Analysis --- p.37Chapter 4.4 --- Second Order Effects --- p.38Chapter 4.4.1 --- Device Mismatch --- p.38Chapter 4.4.2 --- Body Effect --- p.39Chapter 4.5 --- Single-ended to Differential-ended converter --- p.39Chapter 4.6 --- Output Buffer Stage --- p.40Chapter 4.7 --- Noise Theory --- p.41Chapter 4.7.1 --- SSB and DSB Noise Figure --- p.42Chapter 4.7.2 --- Noise Figure --- p.43Chapter Chapter5 --- Simulation Results --- p.44Chapter 5.1 --- Introduction --- p.44Chapter 5.2 --- Current Folded Mirror Mixer --- p.44Chapter 5.2.1 --- Conversion Gain --- p.45Chapter 5.2.2 --- Linearity --- p.46Chapter 5.2.2.1 --- 1dB Compression Point and IIP3 --- p.49Chapter 5.2.3 --- Output Buffer Stage --- p.49Chapter 5.3 --- Current Mode Mixer --- p.51Chapter 5.3.1 --- Conversion Gain --- p.51Chapter 5.3.2 --- Linearity --- p.52Chapter 5.3.2.1 --- 1-dB Compression Point and IIP3 --- p.52Chapter 5.3.3 --- Output Buffer Stage --- p.53Chapter 5.3.4 --- V-I Converter --- p.54Chapter 5.4 --- Single-ended to Differential-ended Converter --- p.55Chapter Chapter6 --- Layout Consideration --- p.57Chapter 6.1 --- Introduction --- p.57Chapter 6.2 --- CMOS transistor Layout --- p.57Chapter 6.3 --- Resistor Layout --- p.59Chapter 6.4 --- Capacitor Layout --- p.60Chapter 6.5 --- Substrate Tap --- p.62Chapter 6.6 --- Pad Layout --- p.63Chapter 6.7 --- Analog Cell Layout --- p.64Chapter Chapter7 --- Measurements --- p.65Chapter 7.1 --- Introduction --- p.65Chapter 7.2 --- Downconversion mixer --- p.66Chapter 7.3 --- PCB Layout --- p.66Chapter 7.4 --- Test Setups --- p.68Chapter 7.4.1 --- Measurement Setup for S-Parameter --- p.68Chapter 7.4.2 --- Measurement Setup for 1-dB Compression Point and IIP3 --- p.70Chapter 7.5 --- Measurement Result of the Current Folded Mirror Mixer --- p.72Chapter 7.5.1 --- S-Parameter Measurement --- p.75Chapter 7.5.2 --- Conversion Gain and the Effect of the IF Variation --- p.77Chapter 7.5.3 --- 1-dB Compression Point --- p.78Chapter 7.5.4 --- IIP3 --- p.79Chapter 7.5.5 --- LO Power Effect to the Mixer --- p.81Chapter 7.5.6 --- Performance Summaries of the Current Folded Mirror Mixer --- p.82Chapter 7.5.7 --- Discussion --- p.83Chapter 7.6 --- Measurement Result of the Current Mode Mixer --- p.84Chapter 7.6.1 --- S-Parameter Measurement --- p.87Chapter 7.6.2 --- Conversion Gain and the Effect of the IF Variation --- p.89Chapter 7.6.3 --- 1-dB Compression Point --- p.90Chapter 7.6.4 --- IIP3 --- p.91Chapter 7.6.5 --- LO Power Effect to the Mixer --- p.93Chapter 7.6.6 --- Performance Summaries of the Current Mode Mixer --- p.94Chapter 7.6.7 --- Discussion --- p.95Chapter 7.7 --- Measurement Result of the Single-ended to Differential-ended converter --- p.96Chapter 7.7.1 --- Measurement Setup for the Phase Difference --- p.97Chapter 7.7.2 --- Phase Difference Measurement --- p.98Chapter 7.7.3 --- Discussion --- p.99Chapter Chapter8 --- Conclusion --- p.100Chapter Appendix A --- Characteristics of the Gilbert Quad Pair --- p.102Chapter A.1 --- Large-Signal Analysis --- p.102Chapter Appendix B --- Characteristics of the V-I Converter --- p.105Chapter B.1 --- Large-Signal Analysis --- p.105Bibliography --- p.10

RF receiver design using the direct conversion approach at 5.8 GHz band based on IEEE 802.11a standard

This thesis presents the development and analysis of a radio frequency (RF) front-end direct conversion receiver at 5.725 – 5.825 GHz where IEEE 802.11a standard is used as performance test. The RF receiver is designed based on the commercialized products (off-the-shelf) where it focuses on the system design tradeoff, rather than circuit design tradeoff. The RF receiver has been designed with the selected architecture where it is consist of low noise amplifier (LNA), radio frequency amplifier (RFA), power divider and two bandpass filters. The modeled RF receiver has been analyzed by using Advanced Design System (ADS) 2005A software for system characteristic and performance test. From the simulation, minimum sensitivity is -91 dBm at data rate 6 Mbps and -74 dBm at data rate 54 Mbps where it is comply with the IEEE 802.11a standard. The RF receiver prototype has been measured and this system produces has gain of 39 dB which is higher than the reviewed of 37.5 dB. The noise figure of this work is measured at 1.30 dB, which is better than the reviewed work at 4.6 dB. The nonlinearity characteristic such as power at 1dB compression point (P1dB) and third order intercept point (IP3) is observed. From the measurement, the RF receiver will drop 1 dB when input power (Pin) is injected above -27 dBm then it caused output power (Pout) start saturated. The third output intercept point (OIP3) and third input intercept point (IIP3) is at around 15 dBm and -24.50 dBm respectively. The RF receiver system characteristic such as sensitivity meet the standard requirement of IEEE 802.11a standard for wireless local area network (WLAN) bridge system.

Dual-band impedance transformation networks for integrated power amplifiers

This paper shows that the two most common impedance transformation networks for power amplifiers (PAs) can be designed to achieve optimum transformation at two frequencies. Hence, a larger bandwidth for the required impedance transformation ratio is achieved. A design procedure is proposed, which takes imperfections like losses into account. Furthermore, an analysis method is presented to estimate the maximum uncompressed output power of a PA with respect to frequency. Based on these results, a fully integrated PA with a dual-band impedance transformation network is designed and its functionality is proven by large signal measurement results. The amplifier covers the frequency band from 450 MHz to 1.2 GHz (3 dB bandwidth of the output power and efficiency), corresponding to a relative bandwidth of more than 100%. It delivers 23.7 dBm output power in the 1 dB compression point, having a power-added efficiency of 33%