Semiconductor ac static power switch

Semiconductor ac static power switch has long life and high reliability, contains no moving parts, and operates satisfactorily in severe environments, including high vibration and shock conditions. Due to their resistance to shock and vibration, static switches are used where accidental switching caused by mechanical vibration or shock cannot be tolerated

Ultra-Low-Power Superconductor Logic

We have developed a new superconducting digital technology, Reciprocal Quantum Logic, that uses AC power carried on a transmission line, which also serves as a clock. Using simple experiments we have demonstrated zero static power dissipation, thermally limited dynamic power dissipation, high clock stability, high operating margins and low BER. These features indicate that the technology is scalable to far more complex circuits at a significant level of integration. On the system level, Reciprocal Quantum Logic combines the high speed and low-power signal levels of Single-Flux- Quantum signals with the design methodology of CMOS, including low static power dissipation, low latency combinational logic, and efficient device count.Comment: 7 pages, 5 figure

The detection of lubricating oil viscosity changes in gearbox transmission systems driven by sensorless variable speed drives using electrical supply parameters

Lubrication oil plays a decisive role to maintain a reliable and efficient operation of gear transmissions. Many offline methods have been developed to monitor the quality of lubricating oils. This work focus on developing a novel online method to diagnose oil degradation based on the measurements from power supply system to the gearbox. Experimental studies based on an 10kW industrial gearbox fed by a sensorless variable speed drive (VSD) shows that measurable changes in both static power and dynamic behaviour are different with lube oils tested. Therefore, it is feasible to use the static power feature to indicate viscosity changes at low and moderate operating speeds. In the meantime, the dynamic feature can separate viscosity changes for all different tested cases

Novel Ternary Logic Gates Design in Nanoelectronics

In this paper, standard ternary logic gates are initially designed to considerably reduce static power consumption. This study proposes novel ternary gates based on two supply voltages in which the direct current is eliminated and the leakage current is reduced considerably. In addition, ST-OR and ST-AND are generated directly instead of ST-NAND and ST-NOR. The proposed gates have a high noise margin near V_(DD)/4. The simulation results indicated that the power consumption and PDP underwent a~sharp decrease and noise margin showed a considerable increase in comparison to both one supply and two supply based designs in previous works. PDP is improved in the proposed OR, as compared to one supply and two supply based previous works about 83% and 63%, respectively. Also, a memory cell is designed using the proposed STI logic gate, which has a considerably lower static power to store logic ‘1’ and the static noise margin, as compared to other designs

Impedance-compensated grid synchronisation for extending the stability range of weak grids with voltage source converters

This paper demonstrates how the range of stable power transfer in weak grids with voltage source converters (VSCs) can be extended by modifying the grid synchronisation mechanism of a conventional synchronous reference frame phase locked loop (PLL). By introducing an impedance-conditioning term in the PLL, the VSC control system can be virtually synchronised to a stronger point in the grid to counteract the instability effects caused by high grid impedance. To verify the effectiveness of the proposed approach, the maximum static power transfer capability and the small-signal stability range of a system with a VSC HVDC terminal connected to a weak grid are calculated from an analytical model with different levels of impedance-conditioning in the PLL. Such calculations are presented for two different configurations of the VSC control system, showing how both the static power transfer capability and the small-signal stability range can be significantly improved. The validity of the stability assessment is verified by time-domain simulations in the Matlab/Simulink environment.Peer ReviewedPostprint (published version

An Energy Efficient Semi-static Power Control and Link Adaptation Scheme in UMTS HSDPA

High speed downlink packet access (HSDPA) has been successfully applied in commercial systems and improves user experience significantly. However, it incurs substantial energy consumption. In this paper, we address this issue by proposing a novel energy efficient semi-static power control and link adaptation scheme in HSDPA. Through estimating the EE under different modulation and coding schemes (MCSs) and corresponding transmit power, the proposed scheme can determine the most energy efficient MCS level and transmit power at the Node B. And then the Node B configure the optimal MCS level and transmit power. In order to decrease the signaling overhead caused by the configuration, a dual trigger mechanism is employed. After that, we extend the proposed scheme to the multiple input multiple output (MIMO) scenarios. Simulation results confirm the significant EE improvement of our proposed scheme. Finally, we give a discussion on the potential EE gain and challenge of the energy efficient mode switching between single input multiple output (SIMO) and MIMO configuration in HSDPA.Comment: 9 pages, 11 figures, accepted in EURASIP Journal on Wireless Communications and Networking, special issue on Green Radi

Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories

In this paper, we show how beneficial effects of aging on static power consumption can be exploited to design reliable drowsy cache memories adopting dynamic voltage scaling(DVS) to reduce static power. First, we develop an analytical model allowing designers to evaluate the long-term threshold voltage degradation induced by bias temperature instability (BTI)in a drowsy cache memory. Through HSPICE simulations, we demonstrate that, as drowsy memories age, static power reduction techniques based on DVS become more effective because of reduction in sub-threshold current due to BTI aging. We develop a simulation framework to evaluate trade-offs between static power and reliability, and a methodology to properly select the “drowsy” data retention voltage. We then propose different architectures of a drowsy cache memory allowing designers to meet different power and reliability constraints. The performed HSPICE simulations show a soft error rate and static noise margin improvement up to 20.8% and 22.7%, respectively, compared to standard aging unaware drowsy technique. This is achieved with a limited static power increase during the very early lifetime, and with static energy saving of up to 37% in 10 years of operation, at no or very limited hardware overhead

Non-volatile Optical Switch Based on a GST-Loaded Directional Coupler

We present a non-volatile optical switch based on a directional coupler comprising a silicon-Ge2Sb2Te5 (GST) hybrid waveguide. The non-volatility of GST makes it attractive for reducing static power consumption in optical switching. Experimental results show that the optical switch has an extinction ratio of >20 dB in the bar state and >25 dB in the cross state around 1578 nm wavelength. The insertion loss is 2 dB and 7 dB for the bar and cross states, respectively

Offset-compensated comparator with full-input range in 150nm FDSOI CMOS-3d technology

This paper addresses an offset-compensated comparator with full-input range in the 150nm FDSOI CMOS- 3D technology from MIT- Lincoln Laboratory. The comparator discussed here makes part of a vision system. Its architecture is that of a self-biased inverter with dynamic offset correction. At simulation level, the comparator can reach a resolution of 0.1mV in an area of approximately 220μm2 with a time response of less than 40ns and a static power dissipation of 1.125μW

Design of an Efficient Interconnection Network of Temperature Sensors

Temperature has become a first class design constraint because high temperatures adversely affect circuit reliability, static power and degrade the performance. In this scenario, thermal characterization of ICs and on-chip temperature monitoring represent fundamental tasks in electronic design. In this work, we analyze the features that an interconnection network of temperature sensors must fulfill. Departing from the network topology, we continue with the proposal of a very light-weight network architecture based on digitalization resource sharing. Our proposal supposes a 16% improvement in area and power consumption compared to traditional approache