A systematic integration of register allocation and instruction scheduling

In order to achieve high performance, processor architecture has become more and more complicated. As a result, compiler-time optimizations have become more and more important for the effective use of a complex processor. One of the promising compiler-time optimizations is the integration of register allocation and instruction scheduling based on register-reuse chains. In the previous approach, however, the generation of register-reuse chains was not completely systematic and consequently created many unnecessary dependencies that restrict instruction scheduling. This research proposes a new register allocation technique based on a systematic generation of register-reuse chains. The first phase of the proposed technique is to generate register-reuse chains that are optimal in the sense that no additional dependencies are created. Thus, register allocation can be done without restricting instruction scheduling. For the case when the optimal register-reuse chains require more than available registers, the second phase reduces the number of required registers by merging the register-reuse chains. A heuristic is developed for the second phase in order to reduce the additional dependencies created by merging chains. The first step of the second phase is to derive a conflict graph in which each node corresponds to a register-reuse chain, while an edge represents where the corresponding two chains cannot be merged. Applying a graph-coloring algorithm to the conflict graph, the number of chains can be effectively reduced. The final step of the second phase is to run the 0-1 knapsack algorithm to make the number of chains exactly the same as the number of available registers. The proposed register allocation is implemented in LCC (Local C Compiler). An instruction scheduler is also implemented in LCC and then integrated with the proposed register allocator. Evaluation results show that the proposed algorithm and heuristic effectively reduce the number of necessary registers

Compilation statique de Java

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal

Estudo e desenvolvimento de sistemas de geração de back-ends do processo de compilação

O back-end de um compilador agrupa todo um conjunto de tarefas cuja implementação é intrinsecamente dependente das características do processador para o qual se pretende gerar código. A rápida evolução da industria dos processadores e microcontroladores levou esta área de desenvolvimento de software a realizar fortes investimentos na pesquisa de meios que permitissem dar uma resposta rápida e de qualidade à procura verificada. É dentro deste contexto que surge o tema e o trabalho desenvolvido ao longo desta tese de mestrado, que pretende de alguma forma sintetizar o que já se encontra feito e propor algumas soluções, que apesar de individualmente não serem originais permitem, quando em conjunto, vislumbrar alternativas aos sistemas já concebidos e avançar um pouco mais na área de investigação dos geradores de código final e optimizadores. O trabalho aqui descrito é extremamente abrangente para uma qualquer tese, cobrindo todas as áreas do processo de compilação a partir da análise semântica até à geração do código máquina, passando pela apresentação de modelos de compiladores, representação da informação, sistemas de análise de fluxo de controlo e de dados, alocação de registos local e global, selecção de instruções e geração de selectores, optimização de código a vários níveis, etc. É ainda de referir que do trabalho desenvolvido resultou o Back-End Development System, que como o nome indica é um sistema de apoio ao desenvolvimento das tarefas de back-end de um compilador. The back-end of a compiler gathers a group of tasks, whose implementation is directly dependent on the features of the processor for which machine code is intended to be generated. The fast evolution of processors and micro-controllers industry lead this area of software development to perform strong investments in the research of means, which would give a fast and proper answer to the demand. It is within this context that the theme and the work carried on through this thesis emerges. The aim of this work is to synthesise what has already been done and to give some solutions which, although individually not original, when put together, they allow alternatives to the pre-established systems and move on a little further in the research of generators of final code and optimisers. This work is extremely wide-ranging, covering all areas of the compiling process, going from the semantic analyses till the generation of machine code. It also contains the presentation of models of compilers, representation of information, control and data flow analysis, local and global registers allocation, instructions selection and generation of selectors, code optimisation at several levels, etc. It is also important to refer that from the development work emerged the Back-End Development System, which, as the name itself indicates, is a software system to support development of back-end tasks of a compiler

Estudo e desenvolvimento de sistemas de geração de back-ends do processo de compilação

O back-end de um compilador agrupa todo um conjunto de tarefas cuja implementação é intrinsecamente dependente das características do processador para o qual se pretende gerar código. A rápida evolução da industria dos processadores e microcontroladores levou esta área de desenvolvimento de software a realizar fortes investimentos na pesquisa de meios que permitissem dar uma resposta rápida e de qualidade à procura verificada. É dentro deste contexto que surge o tema e o trabalho desenvolvido ao longo desta tese de mestrado, que pretende de alguma forma sintetizar o que já se encontra feito e propor algumas soluções, que apesar de individualmente não serem originais permitem, quando em conjunto, vislumbrar alternativas aos sistemas já concebidos e avançar um pouco mais na área de investigação dos geradores de código final e optimizadores. O trabalho aqui descrito é extremamente abrangente para uma qualquer tese, cobrindo todas as áreas do processo de compilação a partir da análise semântica até à geração do código máquina, passando pela apresentação de modelos de compiladores, representação da informação, sistemas de análise de fluxo de controlo e de dados, alocação de registos local e global, selecção de instruções e geração de selectores, optimização de código a vários níveis, etc. É ainda de referir que do trabalho desenvolvido resultou o Back-End Development System, que como o nome indica é um sistema de apoio ao desenvolvimento das tarefas de back-end de um compilador. The back-end of a compiler gathers a group of tasks, whose implementation is directly dependent on the features of the processor for which machine code is intended to be generated. The fast evolution of processors and micro-controllers industry lead this area of software development to perform strong investments in the research of means, which would give a fast and proper answer to the demand. It is within this context that the theme and the work carried on through this thesis emerges. The aim of this work is to synthesise what has already been done and to give some solutions which, although individually not original, when put together, they allow alternatives to the pre-established systems and move on a little further in the research of generators of final code and optimisers. This work is extremely wide-ranging, covering all areas of the compiling process, going from the semantic analyses till the generation of machine code. It also contains the presentation of models of compilers, representation of information, control and data flow analysis, local and global registers allocation, instructions selection and generation of selectors, code optimisation at several levels, etc. It is also important to refer that from the development work emerged the Back-End Development System, which, as the name itself indicates, is a software system to support development of back-end tasks of a compiler

An Architecture for the Compilation of Persistent Polymorphic Reflective Higher-Order Languages

Persistent Application Systems are potentially very large and long-lived application systems which use information technology: computers, communications, networks, software and databases. They are vital to the organisations that depend on them and have to be adaptable to organisational and technological changes and evolvable without serious interruption of service. Persistent Programming Languages are a promising technology that facilitate the task of incrementally building and maintaining persistent application systems. This thesis identifies a number of technical challenges in making persistent programming languages scalable, with adequate performance and sufficient longevity and in amortising costs by providing general services. A new architecture to support the compilation of long-lived, large-scale applications is proposed. This architecture comprises an intermediate language to be used by front-ends, high-level and machine independent optimisers, low-level optimisers and code generators of target machine code. The intermediate target language, TPL, has been designed to allow compiler writers to utilise common technology for several different orthogonally persistent higher-order reflective languages. The goal is to reuse optimisation and code-generation or interpretation technology with a variety of front-ends. A subsidiary goal is to provide an experimental framework for those investigating optimisation and code generation. TPL has a simple, clean type system and will support orthogonally persistent, reflective, higher-order, polymorphic languages. TPL allows code generation and the abstraction over details of the underlying software and hardware layers. An experiment to build a prototype of the proposed architecture was designed, developed and evaluated. The experimental work includes a language processor and examples of its use are presented in this dissertation. The design space was covered by describing the implications of the goals of supporting the class of languages anticipated while ensuring long-term persistence of data and programs, and sufficient efficiency. For each of the goals, the design decisions were evaluated in face of the results

Register Allocation over the Program Dependence Graph

This paper describes RAP, a Register Allocator that allocates registers over the Program Dependence Graph (PDG) representation of a program in a hierarchical manner. The PDG program representation has been used successfully for scalar optimizations, the detection and improvement of parallelism for vector machines, multiple processor machines, and machines that exhibit instruction level parallelism, as well as debugging, the integration of different versions of a program, and translation of imperative programs for data flow machines. By basing register allocation on the PDG, the register allocation phase may be more easily integrated and intertwined with other optimization analyses and transformations. In addition, the advantages of a hierarchical approach to global register allocation can be attained without constructing an additional structure used solely for register allocation. Our experimental results have shown that on average, code allocated registers via RAP executed 2.7% faster..