50-nm self-aligned and 'standard' T-gate InP pHEMT comparison: the influence of parasitics on performance at the 50-nm node

Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In0.7Ga0.3As channel 50-nm self-aligned and "standard" T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT syste

50-nm T-gate metamorphic GaAs HEMTs with f_T of 440 GHz and noise figure of 0.7 dB at 26 GHz

GaAs-based transistors with the highest f/sub T/ and lowest noise figure reported to date are presented in this letter. A 50-nm T-gate In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As metamorphic high-electron mobility transistors (mHEMTs) on a GaAs substrate show f/sub T/ of 440 GHz, f/sub max/ of 400 GHz, a minimum noise figure of 0.7 dB and an associated gain of 13 dB at 26 GHz, the latter at a drain current of 185 mA/mm and g/sub m/ of 950 mS/mm. In addition, a noise figure of below 1.2 dB with 10.5 dB or higher associated gain at 26 GHz was demonstrated for drain currents in the range 40 to 470 mA/mm at a drain bias of 0.8 V. These devices are ideal for low noise and medium power applications at millimeter-wave frequencies

50 nm GaAs mHEMTs and MMICs for ultra-low power distributed sensor network applications

We report well-scaled 50 nm GaAs metamorphic HEMTs (mHEMTs) with DC power consumption in the range 1-150 ΜW/Μ demonstrating f<sub>T</sub> of 30-400 GHz. These metrics enable the realisation of ultra-low power (<500 ΜW) radio transceivers for autonomous distributed sensor network applications

Monte Carlo simulations of high-performance implant free In_0.3Ga_0.7 nano-MOSFETs for low-power CMOS applications

No abstract available

Very high performance 50 nm T-gate III-V HEMTs enabled by robust nanofabrication technologies

In this paper, we review a range of nanofabrication techniques which enable the realization of uniform, high yield, high performance 50 nm T-gate III-V high electron mobility transistors (HEMTs). These technologies have been applied in the fabrication of a range of lattice matched and pseudomorphic InP HEMTs and GaAs metamorphic HEMTs with functional yields in excess of 95%, threshold voltage uniformity of 5 mV, DC transconductance of up to 1600 mS/mm and f/sub T/ of up to 480 GHz. These technologies and device demonstrators are key to enabling a wide range of millimeter-wave imaging and sensing applications beyond 100 GHz, particularly where array-based multi-channel solutions are required

180nm metal gate, high-k dielectric, implant-free III--V MOSFETs with transconductance of over 425 μS/μm

Abstract: Data is reported from 180 nm gate length GaAs n-MOSFETs with drive current (Ids,sat) of 386 μA/μm (Vg=Vd =1.5 V), extrinsic transconductance (gm) of 426 μS/μm, gate leakage ( jg,limit) of 44 nA/cm2, and on resistance (Ron) of 1640 Ω μm. The gm and Ron metrics are the best values reported to date for III-V MOSFETs, and indicate their potential for scaling to deca-nanometre dimensions

An overview on recent developments in RF and microwave power H-terminated diamond MESFET technology

Thanks to its wide bandgap, exceptionally high thermal conductivity and relatively high carrier velocities, diamond exhibits attractive semiconductor properties that make it an interesting candidate for high power, high frequency and high temperature solid-state microelectronic devices, able to withstand harsh environmental conditions (in terms of temperature and/or radiation). The development of a diamond transistor technology has been restricted for many years due to the difficulty in implementing conventional acceptor or donor bulk doping strategies with satisfactory activation at room temperature. More recently, a breakthrough in diamond MESFET technology was represented by the introduction of surface diamond p-doping by means of H-termination, opening the way to interesting development in the microwave field. The paper presents an overview on recent developments in H-terminated diamond MESFETs for power RF and microwave applications. After an introduction to the diamond technology and device state-of-the-art performance, the physics-based and large-signal modeling of diamond MESFETs is discusse

Sub-micron, Metal Gate, High-к Dielectric, Implant-free, Enhancement-mode III-V MOSFETs

The performance of 300nm, 500nm and 1μm metal gate, implant free, enhancement mode III-V MOSFETs are reported. Devices are realised using a 10nm MBE grown Ga2O3/(GaxGd1-x)2O3 high-κ (κ=20) dielectric stack grown upon a δ-doped AlGaAs/InGaAs/AlGaAs/GaAs heterostructure. Enhancement mode operation is maintained across the three reported gate lengths with a reduction in threshold voltage from 0.26 V to 0.08 V as the gate dimension is reduced from 1 μm to 300 nm. An increase in transconductance is also observed with reduced gate dimension. Maximum drain current of 420 μA/μm and extrinsic transconductance of 400 µS/µm are obtained from these devices. Gate leakage current of less than 100pA and subthreshold slope of 90 mV/decade were obtained for all gate lengths. These are believed to be the highest performance submicron enhancement mode III-V MOSFETs reported to date

1 μm gate length, In_0.75Ga_0.25As channel, thin body n-MOSFET on InP substrate with transconductance of 737μS/μm

The first demonstration of implant-free, flatband-mode In<sub>0.75</sub>Ga<sub>0.25</sub>As channel n-MOSFETs is reported. These 1 μm gate length MOSFETs, fabricated on a structure with average mobility of 7720 cm<sup>2</sup>/Vs and sheet carrier concentration of 3.3×10<sup>12</sup> cm<sup>-22</sup>, utilise a Pt gate, a high-k dielectric (k≈20), and a δ-doped InAlAs/InGaAs/InAlAs heterostructure. The devices have a typical maximum drive current (I<sub>d,sat</sub>) of 933 μA/μm, extrinsic transconductance (g<sub>m</sub>) of 737 μS/μm, gate leakage (I<sub>g</sub>) of 40 pA, and on-resistance (R<sub>on</sub>) of 555 Ωμm. The g<sub>m</sub> and R<sub>on</sub> figures of merit are the best reported to date for any III-V MOSFET

High Mobility III-V MOSFETs For RF and Digital Applications

Developments over the last 15 years in the areas of materials and devices have finally delivered competitive III-V MOSFETs with high mobility channels. This paper briefly reviews the above developments, discusses properties of the GdGaO/Ga2O3 MOS systems, presents GaAs MOSFET DC and RF data, and concludes with an outlook for high indium content channel MOSFETs. GaAs based MOSFETs are potentially suitable for RF power amplification, switching, and front-end integration in mobile and wireless applications while MOSFETs with high indium content channels are of interest for future CMOS applications