Abstract:

Data is reported from 180 nm gate length GaAs n-MOSFETs with drive current (Ids,sat) of 386 μA/μm (Vg=Vd =1.5 V), extrinsic transconductance (gm) of 426 μS/μm, gate leakage ( jg,limit) of 44 nA/cm2, and on resistance (Ron) of 1640 Ω μm. The gm and Ron metrics are the best values reported to date for III-V MOSFETs, and indicate their potential for scaling to deca-nanometre dimensions

Droopad, R.

Hill, R.J.W.

Li, X.

Macintyre, D.

Moran, D.A.J.

Passlack, M.

Thayne, I.G.

Thoms, S.

Zhou, H.

English

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      Hill, R.J.W. and Moran, D.A.J. and Li, X. and Zhou, H. and Macintyre, D. and Thoms, S. and Droopad, R. and Passlack, M. and Thayne, I.G. (2007) 180 nm metal gate, high-k dielectric, implant free III-V MOSFETs with transconductance of over 425μS/μm. Electronics Letters 43:pp. 543-545.        http://eprints.gla.ac.uk/4145/  Deposited on: 6 May 2008   Glasgow ePrints Service http://eprints.gla.ac.uk 180 nm metal gate, high-k dielectric, implant free III-V MOSFETs with transconductance of over 425μS/μm  Richard J.W. Hill, David .A.J. Moran, Xu Li, Haiping Zhou, Douglas Macintyre, Stephen Thoms, Ravi Droopad, Matthias Passlack, Iain G. Thayne.   Abstract: We report data from 180 nm gate length GaAs n-MOSFETs with drive current (Ids,sat) of 386 μA/μm (Vg = Vd = 1.5 V), extrinsic transconductance (gm) of 426 μS/μm, gate leakage (Jg,limit) of 44 nA/cm2, and on resistance (Ron) of 1640 Ω.μm. The gm and Ron metrics are the best values reported to date for III-V MOSFETs, and indicates their potential for scaling  to deca-nanometre dimensions.  Introduction: Novel device architectures, high-k gate dielectrics, metal gates and high mobility channel materials will be required to continue CMOS device scaling according to Moore’s Law and the ITRS [1, 2]. It is now widely accepted that high mobility channel materials are likely to be required beyond the 22 nm node and for this reason, activity has escalated in both Ge-based p-MOSFET and III-V-based n-MOSFET device research [3]. The potential benefits of III-V n-MOSFETs [4] have been explored extensively by Monte Carlo simulations [5], and include significantly higher drive current at lower supply voltage compared with silicon-based devices for a given device geometry. The lack of a device quality III-V semiconductor/insulator interface has, in the past, prevented the exploitation of the high electron mobility of compound semiconductors in MOSFETs [6-8], but recent  progress using an in-situ MBE grown Ga2O3/(GaxGd1-x)2O3 (GGO) stack has demonstrated the long channel potential of this technology [9-12]. The implant-free flat-band architecture described in [11] uses a modulation doped channel to provide connection between the ohmic contacts and the gate, where enhancement mode (e-mode) operation is achieved through judicious selection of gate metal work-function and doping strategy in a high electron mobility III-V heterostructure.  Layer structure and device fabrication: Material growth was carried out on a 3" semi-insulating GaAs substrate using a dual chamber molecular beam epitaxy (MBE) system by the method detailed in [9]. The III-V heterostructure was grown in one chamber before being transferred under ultra high vacuum to a second chamber for high-κ dielectric deposition. Fig. 1 gives the layer compositions and dimensions of the III-V MOSFET structure. A two-level wrap-around gate design (where the gate encircles the drain) was used to simplify the device process flow, removing the need for isolation. The source-drain separation was 1.65 μm. Both the gate (Pt/Au) and ohmic contacts (Ni/Ge/Au) were defined by direct write e-beam lithography and patterned by the lift-off method. The GGO dielectric was removed by wet chemical etching prior to deposition of the ohmic contacts, which underwent rapid thermal annealing at 430°C for 60 s.  Transmission line measurement (TLM) data obtained from process control structures alongside the devices gave a contact resistance (Rc) of 470 Ω.μm and a sheet resistance (Rsh) of 433 Ω/sq.  Results: Fig. 2 gives typical output characteristics of the 180 nm gate length devices, the shortest gate length III-V MOSFET thus far reported. These well behaved devices have Ron (which at this device geometry can be used as a first order approximation for parasitic series resistance) of 1640 Ω.μm - the lowest value reported to date [13]. For the given device geometry, this is in close agreement with the value calculated from the Rc and Rsh values extracted from TLM structures (1650 Ω.μm).  Typical transfer characteristics, given in Fig. 3, exhibit a threshold voltage (Vt) of -0.47 V,  a maximum drain-source saturation current (Ids,sat) of 386 μA/μm, and a peak extrinsic transconductance of 426 μS/μm, - the highest value reported to date [12]. We expect that with relatively minor refinements to the gate metal effective work-function, gate-to-channel separation or doping strategy, a positive Vt and e-mode operation can be achieved. The gate leakage at Vgs = Vds = 1.5 V (Jg,limit) was 44 nA/cm2.  Fig. 4 compares the extrinsic gm with previously published data for III-V MOSFETs. This work and [12, 14-17] were carried out on GaAs wafers, but [13] used an InP substrate, allowing the use of a higher indium concentration channel with higher mobility, which should translate into higher drive current and higher transconductance. Despite this, the data presented in this letter represents an increase in gm of 68% over the previously published best results [12].  Conclusion:  In this letter, we have presented data on the shortest gate length III-V MOSFETs realised to date. These devices have the highest gm (68% improvement on recently achieved results [12]) and lowest Ron (34% lower than previous best result [13]) reported, and demonstrate the potential for scaling III-V MOSFETs to deca-nanometre dimensions.       Authors’ affiliations: R. Hill, D. Moran, X. Li , H. Zhou, D.Macintyre, S. Thoms, and I. Thayne are with the Nanoelectronics Research Centre, University of Glasgow, Rankine Building, Oakfield Avenue, Glasgow, G12 8LT (e-mail: r.hill@elec.gla.ac.uk) M. Passlack and R. Droopad are with Freescale Semiconductor Inc., Tempe, AZ 85284 USA  Acknowledgements: We are grateful to Asen Asenov and Colin Stanley for stimulating discussions and to the UK Engineering and Physical Sciences Research Council and the Scottish Funding Council who have funded this work.     Figure captions:   Fig. 1  III-V MOSFET layer structure.   Fig. 2  Output characteristics of a typical 180 nm gate length III-V MOSFET.   Fig. 3  Transfer characteristics of a typical 180 nm gate length III-V MOSFET (Vd = 1.5V).    Fig. 4 Comparison of published III-V MOSFET gm with values obtained in this work.       10nm GGO10nm In0.3Ga0.7As -Channel65nm Al0.2Ga0.8As - Bufferδ − doping2nm Al0.45Ga0.55As - Barrier3nm Al0.2Ga0.8As  - Spacer200nm GaAs - Buffer3nm GaAs - Spacer2 nm GaAs - SpacerGaAs SI Substrate Figure 1   0.0 0.5 1.0 1.50100200300400I ds (μA/μm)Vds (V)-0.500.511.5Vgs=(V) Figure 2  -0.5 0.0 0.5 1.0 1.50100200300400Vgs (V)I ds (μA/μm)0100200300400gm  (μS/μm) Figure 3 0.1 1 100100200300400500[12]g m(μS/μm)Lg (μm)[This work][17] [14][13][11] [15][16] Figure 4    References 1. Moore, G.E., Cramming more Components onto Integrated Circuits. Electronics, 1965. 38(8). 2. Process Integration, Devices, and Structures, in International Technology Roadmap for Semiconductors. 2005, ITRS. p. 11. 3. www.src.org/member/news/center_cmos06.asp. 4. Pethe, A., T. Krishnamohan, K. Donghyun, O. Saeroonter, H.S.P. Wong, Y. Nishi, and K.C. Saraswat. Investigation of the performance limits of III-V double-gate n-MOSFETs. in IEDM Tech. Dig. 2005. 5. Kalna, K., J.A. Wilson, D.A.J. Moran, R.J.W. Hill, A.R. Long, R. Droopad, M. Passlack, I.G. Thayne, and A. Asenov, Monte Carlo Simulations of High-Performance Implant Free In0.3Ga0.7As Nano-MOSFETs for Low-Power CMOS Applications. Nanotechnology, IEEE Transactions on, 2007. 6(1): p. 106. 6. Becke, H., R. Hall, and J. White, Gallium arsenide MOS transistors. Solid-State Electronics, 1965. 8(10): p. 812-818. 7. Croydon, W.F. and E.H.C. Parker, Dielectric Films on Gallium Arsenide. 1981, New York: Gordon and Breach Scientific Publishers. 8. Mimura, T. and M. Fukuta, Status of the GaAs metal-oxide-semiconductor technology. Electron Devices, IEEE Transactions on, 1980. 27(6): p. 1147-55. 9. Passlack, M., J.K. Abrokwah, and R. Droopad, Development methodology for high-k gate dielectrics on III-V semiconductors:GdxGa0.4-xO0.6/Ga2O3 dielectric stacks on GaAs. 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Demonstration of submicron depletion-mode GaAs MOSFET's with negligible drain current drift and hysteresis.

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Ga2O3/Gd2O3/InGaAs enhancement-mode nchannel MOSFETs.

GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition.

GaAs MOSFET's fabrication with a selective liquid phase oxidized gate.

Gallium arsenide MOS transistors. Solid-State Electronics,

Implant-free high-mobility flatband MOSFET: principles of operation. Electron Devices,

Investigation of the performance limits of III-V double-gate n-MOSFETs.

Monte Carlo Simulations of High-Performance Implant Free In0.3Ga0.7As Nano-MOSFETs for Low-Power CMOS Applications. Nanotechnology,

Self-aligned GaAs p-channel enhancement mode MOS heterostructure field-effect transistor.

Status of the GaAs metal-oxide-semiconductor technology. Electron Devices,

180nm metal gate, high-k dielectric, implant-free III--V MOSFETs with transconductance of over 425 μS/μm

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http://eprints.gla.ac.uk/4145/1/Moran4145.pdf

180nm metal gate, high-k dielectric, implant-free III--V MOSFETs with transconductance of over 425 μS/μm

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