Exploiting Outer Loops Vectorization in High Level Synthesis

Synthesis of DoAll loops is a key aspect of High Level Synthesis since they allow to easily exploit the potential parallelism provided by programmable devices. This type of parallelism can be implemented in several ways: by duplicating the implementation of body loop, by exploiting loop pipelining or by applying vectorization. In this paper a methodology for the synthesis of complex DoAll loops based on outer vectorization is proposed. Vectorization is not limited to the innermost loops: complex constructs such as nested loops, conditional constructs and function calls are supported. Experimental results on parallel benchmarks show up to 7.35x speed-up and up to 40 % reduction of area-delay product

Long-term stable compressive elastocaloric cooling system with latent heat transfer

Elastocaloric cooling systems can evolve into an environmentally friendly alternative to compressor-based cooling systems. One of the main factors preventing its application is a poor long-term stability of the elastocaloric material. This especially applies to systems that work with tensile loads and which benefit from the large surface area for heat transfer. Exerting compressive instead of tensile loads on the material increases long-term stability-though at the expense of cooling power density. Here, we present a heat transfer concept for elastocaloric systems where heat is transferred by evaporation and condensation of a fluid. Enhanced heat transfer rates allow us to choose the sample geometry more freely and thereby realize a compression-based system showing unprecedented long-term stability of 10$^{7}$ cycles and cooling power density of 6270 W kg$^{-1}$

Runtime asynchronous fault tolerance via speculation

Transient faults are emerging as a critical reliability concern in modern microprocessors. Redundant hardware solutions are commonly deployed to detect transient faults, but they are less flexible and cost-effective than software solutions. However, software solutions are rendered impractical because of high performance overheads. To address this problem, this paper presents Runtime Asynchronous Fault Tolerance via Speculation (RAFT), the fastest transient fault detection technique known to date. Serving as a layer between the application and the underlying platform, RAFT automatically generates two symmetric program instances from a program binary. It detects transient faults in a non-invasive way and exploits high-confidence value speculation to achieve low runtime overhead. Evaluation on a commodity multicore system demonstrates that RAFT delivers a geomean performance overhead of 2.83% on a set of 30 SPEC CPU benchmarks and STAMP benchmarks. Compared with existing transient fault detection techniques, RAFT exhibits the best performance and fault coverage, without requiring any change to the hardware or the software applications

New Results From CLEO and BES

Latest experimental results from BES in the charmonium mass region, and those from CLEO in the bottomonium and charmonium spectroscopy are reviewed.Comment: 12 pages, 12 figures, Presented at First Meeting of the APS Topical Group on Hadron Physics, Fermilab, Batavia, Illinois, Oct 24-26, 200

Precursor proteins in transit through mitochondrial contact sites interact with hsp70 in the matrix

We previously reported that hsp70 in the mitochondrial matrix (mt-hsp70 = Ssc1p) is required for import of precursor proteins destined for the matrix or intermembrane space. Here we show that mt-hsp70 is also needed for the import of mitochondrial inner membrane proteins. In particular, the precursor of ADP/ATP carrier that is known not to interact with hsp60 on its assembly pathway requires functional mt-hsp70 for import, suggesting a general role of mt-hsp70 in membrane translocation of precursors. Moreover, a precursor arrested in contact sites was specifically co-precipitated with antibodies directed against mt-hsp70. We conclude that mt-hsp70 is directly involved in the translocation of many, if not all, precursor proteins that are transported across the inner membrane

Transport of proteins into the various subcompartments of mitochondria

The import of proteins into mitochondria is an intricate process comprised of multiple steps. The first step involves the sorting of cytosolically synthesized precursor proteins to the mitochondrial surface. There precursor proteins are recognized by specific receptors which deliver them to the general import site present in the outer membrane. The second stage of import involves a series of complex intraorganelle sorting events which results in the delivery of the proteins to one of the four possible submitochondrial destinations, namely the outer and inner membranes, the matrix and intermembrane space. Here in this review, we discuss the current knowledge on these intramitochondrial sorting events. We especially focus on targetting of proteins to the intermembrane space. Sorting to the intermembrane space represents a particularly interesting situation, as at least three separate targetting pathways to this subcompartment are known to exist

Effectiveness of one-to-one peer support for patients with severe mental illness - a randomised controlled trial

This project was part of the ‘psychenet’ project (www.psychenet.de) and received funding from the Federal Ministry of Education and Research in Germany from 2011 until 2015 (BMBF-Nr: O1KQ1002B). The project had further study arms that employed qualitative methods as process evaluation that will be published separately

A typology of modifications to peer support work for adults with mental health problems:systematic review

© The Authors 2020. Background Peer support work roles are being implemented internationally, and increasingly in lower-resource settings. However, there is no framework to inform what types of modifications are needed to address local contextual and cultural aspects. Aims To conduct a systematic review identifying a typology of modifications to peer support work for adults with mental health problems. Method We systematically reviewed the peer support literature following PRISMA guidelines for systematic reviews (registered on PROSPERO (International Prospective Register of Systematic Reviews) on 24 July 2018: CRD42018094832). All study designs were eligible and studies were selected according to the stated eligibility criteria and analysed with standardised critical appraisal tools. A narrative synthesis was conducted to identify types of, and rationales for modifications. Results A total of 15 300 unique studies were identified, from which 39 studies were included with only one from a low-resource setting. Six types of modifications were identified: role expectations; initial training; type of contact; role extension; workplace support for peer support workers; and recruitment. Five rationales for modifications were identified: to provide best possible peer support; to best meet service user needs; to meet organisational needs, to maximise role clarity; and to address socioeconomic issues. Conclusions Peer support work is modified in both pre-planned and unplanned ways when implemented. Considering each identified modification as a candidate change will lead to a more systematic consideration of whether and how to modify peer support in different settings. Future evaluative research of modifiable versus non-modifiable components of peer support work is needed to understand the modifications needed for implementation among different mental health systems and cultural settings. Declaration of interest None

The H1 Forward Proton Spectrometer at HERA

The forward proton spectrometer is part of the H1 detector at the HERA collider. Protons with energies above 500 GeV and polar angles below 1 mrad can be detected by this spectrometer. The main detector components are scintillating fiber detectors read out by position-sensitive photo-multipliers. These detectors are housed in so-called Roman Pots which allow them to be moved close to the circulating proton beam. Four Roman Pot stations are located at distances between 60 m and 90 m from the interaction point.Comment: 20 pages, 10 figures, submitted to Nucl.Instr.and Method

Coarse-grained reconfigurable array architectures

Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code