Design and test of the final ALICE SDD CARLOS end ladder board

The paper presents the design and test of the final prototype of the CARLOS (Compression And Run Length Encoding Subsystem) end ladder board that is going to be used in the ALICE experiment at CERN. This board is able to compress data coming from one Silicon Drift Detector (SDD) front-end electronics and to send them towards the data concentrator card CARLOSrx in counting room via a 800 Mb/s optical link. The board design faces several constraints, mainly size (54x49 mm) and radiation tolerance: for this reason the board contains several CERN developed ASICs. A test setup has been realized for selecting the good devices among the 500 cards already produced

浅论《立秋》开放式结局对该剧悲剧意味的深化

CARLOSv3 is the third version of a chip that plays a significant role in the data acquisition chain of the A Large Ion Collider Experiment (ALICE) silicon drift detector (SDD). ALICE is one of the foremost high-energy physics experiments (HEPE) conducted within the Large Hadron Collider at CERN, the European Organization for Nuclear Research in Geneva. CARLOSv3 was principally designed and built for the on-line compression of the input dataset originating from a physical bidimensional silicon sensor. To compress a bidimensional dataset, a bidimensional data compressor was required. The compressor was designed for the ALICE SDD Experiment but could be applied to all experiments in which an incoming stream dataset originates from a bidimensional sensor

A multi-channel trigger and acquisition board for TDC-based readout: Application to the cosmic rays detector of the PolarQuEEEst 2018 project

In the summer of 2018, the PolarQuEEEst experiment accomplished a measurement of cosmic rays flux in the Arctic. The detector, installed on a sailboat, was based on scintillation tiles read by a total of 16 SiPM. A multi-channel board (called TRB) has been designed to process the discriminated SiPM signals providing both self-trigger capability and time-to-digital conversion; it was based on a Cyclone-V Intel FPGA. Time-to-digital conversion has been implemented both into FPGA and with the HPTDC chip (as a backup). In this document the board will be described, enlightening the main features and the achieved performance. Lastly, the PolarQuEEEst measurement campaigns will be briefly described, showing how the TRB board has proved to be effective for experiments which require low power consumption, integration with position and environmental sensors and great portability as well. Final thoughts on future improvements will be also discussed

Recent Developments on the Silicon Drift Detector readout scheme for the ALICE Inner Tracking System

Proposal of abstract for LEB99, Snowmass, Colorado, 20-24 September 1999Recent developments of the Silicon Drift Detector (SDD) readout system for the ALICE Experiment are presented. The foreseen readout system is based on 2 main units. The first unit consists of a low noise preamplifier, an analog memory which continuously samples the amplifier output, an A/D converter and a digital memory. When the trigger signal validates the analog data, the ADCs convert the samples into a digital form and store them into the digital memory. The second unit performs the zero suppression/data compression operations. In this paper the status of the design is presented, together with the test results of the A/D converter, the multi-event buffer and the compression unit prototype.Summary:In the Inner Tracker System (ITS) of the ALICE experiment the third and the fourth layer of the detectors are SDDs. These detectors provide the measurement of both the energy deposition and the bi-dimensional position of the track. In terms of readout an SDD can be viewed as a matrix, where the rows are the detector anodes and the columns are the samples to be read during the drift time; therefore, a very large amount of data has to be amplified, converted in digital form and preprocessed in order to avoid the storage of non-significatn data.Since the electron mobility is a strong temperature function, detector temperature has to be kept constant; on the other hand, it is not possible to use very efficient cooling systems because the amount of material in this area is very limited, so the power budget for the electronic readout is very low (less than 6 mW/anode).The simplest solution would be to send the analog signals outside the sensitive area immediately after a preamplification; unfortunately, the ratio between the number of channels (around 200 000) and the space available is so high that the simple solution of sending all the SDD anodes output outside teh detector zone after a low-noise amplification is not practically manageable.Abstract:The adopted solution is based on three main units:(i) A front-end chip that performs low noise amplification, fast analog storage and A/D conversion(ii) A multi-event digital buffer for data derandomization(iii) A data compression/zero suppression and system control boardThe first two units are distributed on the ladders near the detectors and have stringent power and space requirements, while the third unit is placed at both ends of the ladders and in boxes placed on both ends of the TPC detector.The first unit is the most critical part of the system. It works as follows: the detector signals are continuously amplified, sampled and stored in the analog memory with a frequency of 40 MSamples/s The L0d trigger signal stops the write operation, while the L1 trigger signal starts the conversion phase. This phase will continue until the event data are stored in the event buffer if the L2y confirm trigger signal is received, or rejected if the L2n abort signal will be issued by the trigger system.Prototypes of the three parts have been designed and tested while the full chip is currently under design. Tests of the A/D converter will be presented.The multi-event buffer purpose is to de-randomize the even data in order to reduce the transmission speed. Preliminary tests of the first prototype will be presented.The board placed at the end of the ladders performs various functions. It reduces the amount of data through various cascaded algorithms with variable parameters and transmits the data to the SIU board. It also controls the test and slow control system for the ladder circuitry. Tests of the FPGA-based prototypes will be presented.Special care has been taken for the test problem. The ASICs designed are provided of a test control port based on teh IEEE 1149.1 JTAG standard. The same protocol is used for downloading configuration information

Test Results of the ALICE SDD Electronic Readout Prototypes

The first prototypes of the front-end electronics of the ALICE silicon driftdetectors have been designed and tested. The integrated circuits have been designed using state of the art technologies and, for the analog parts, with radiation-tolerantdesign techniques. In this paper, the test results of the building blocks of the PASCAL chip and the first prototype of the AMBRA chip are presented. The prototypes fully respect the ALICE requirements; owingto the use of deep-submicron technologies together with radiation-tolerant layout techniques, the prototypes have shown a toleranceto a radiation dose much higher than the one foreseen for the ALICE environment.(Abstract only available, full text to follow)

The Silicon Drift Detector readout scheme for the Inner Tracking System of the ALICE Experiment

Presentation at Quark Matter '99, Torino, Italy, 10-15 May 1999The Silicon Drift Detectors (SDDs) provide, through the measurement of the drift time of the charge deposited by the particle which crosses the detector, information on the impact point and on the energy deposition. The foreseen readout scheme is based on a single chip implementation of an integrated circuit that includes low-noise amplification, fast analog strorage and analog to digital conversion, thus avoiding the problems related to the analog signal transmission. A multi-event buffer that reduces the transmission bandwidth and a data compression/zero suppression unit complete the architecture.Abstract:In this paper, the system components design is described, together with the results of the first prototypes

A simulation tool for MRPC telescopes of the EEE project

The Extreme Energy Events (EEE) Project is mainly devoted to the study of the secondary cosmic ray radiation by using muon tracker telescopes made of three Multigap Resistive Plate Chambers (MRPC) each. The experiment consists of a telescope network mainly distributed across Italy, hosted in different building structures pertaining to high schools, universities and research centers. Therefore, the possibility to take into account the effects of these structures on collected data is important for the large physics programme of the project. A simulation tool, based on GEANT4 and using GEMC framework, has been implemented to take into account the muon interaction with EEE telescopes and to estimate the effects on data of the structures surrounding the experimental apparata.A dedicated event generator producing realistic muon distributions, detailed geometry and microscopic behavior of MRPCs have been included to produce experimental-like data. The comparison between simulated and experimental data, and the estimation of detector resolutions is here presented and discussed

Performance of the readout system of the ALICE Zero Degree Calorimeters in LHC Run 3

The ALICE Zero Degree Calorimeters (ZDC) provide information about event geometry in heavy-ion collisions through the detection of spectator nucleons and allow to estimate the delivered luminosity. They are also very useful in p–A collisions, allowing an unbiased estimation of collision centrality. The Run 3 operating conditions will involve a tenfold increase in instantaneous luminosity in heavy-ion collisions, with event rates that, taking into account the different processes, could reach 5 MHz in the ZDCs. The challenges posed by this demanding environment lead to a redesign of the readout system and to the transition to a continuous acquisition. The new system is based on 12 bit, 1 Gsps FMC digitizers that will continuously sample the 26 ZDC channels. Triggering, pedestal estimation and luminosity measurements will be performed on FPGA directly connected to the front-end. The new readout system and the performances foreseen in Run 3 are presented

Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.Comment: 45 pages, 30 figures, submitted to JINS