Proposal of abstract for LEB99, Snowmass, Colorado, 20-24 September 1999Recent developments of the Silicon Drift Detector (SDD) readout system for the ALICE Experiment are presented. The foreseen readout system is based on 2 main units. The first unit consists of a low noise preamplifier, an analog memory which continuously samples the amplifier output, an A/D converter and a digital memory. When the trigger signal validates the analog data, the ADCs convert the samples into a digital form and store them into the digital memory. The second unit performs the zero suppression/data compression operations. In this paper the status of the design is presented, together with the test results of the A/D converter, the multi-event buffer and the compression unit prototype.Summary:In the Inner Tracker System (ITS) of the ALICE experiment the third and the fourth layer of the detectors are SDDs. These detectors provide the measurement of both the energy deposition and the bi-dimensional position of the track. In terms of readout an SDD can be viewed as a matrix, where the rows are the detector anodes and the columns are the samples to be read during the drift time; therefore, a very large amount of data has to be amplified, converted in digital form and preprocessed in order to avoid the storage of non-significatn data.Since the electron mobility is a strong temperature function, detector temperature has to be kept constant; on the other hand, it is not possible to use very efficient cooling systems because the amount of material in this area is very limited, so the power budget for the electronic readout is very low (less than 6 mW/anode).The simplest solution would be to send the analog signals outside the sensitive area immediately after a preamplification; unfortunately, the ratio between the number of channels (around 200 000) and the space available is so high that the simple solution of sending all the SDD anodes output outside teh detector zone after a low-noise amplification is not practically manageable.Abstract:The adopted solution is based on three main units:(i) A front-end chip that performs low noise amplification, fast analog storage and A/D conversion(ii) A multi-event digital buffer for data derandomization(iii) A data compression/zero suppression and system control boardThe first two units are distributed on the ladders near the detectors and have stringent power and space requirements, while the third unit is placed at both ends of the ladders and in boxes placed on both ends of the TPC detector.The first unit is the most critical part of the system. It works as follows: the detector signals are continuously amplified, sampled and stored in the analog memory with a frequency of 40 MSamples/s The L0d trigger signal stops the write operation, while the L1 trigger signal starts the conversion phase. This phase will continue until the event data are stored in the event buffer if the L2y confirm trigger signal is received, or rejected if the L2n abort signal will be issued by the trigger system.Prototypes of the three parts have been designed and tested while the full chip is currently under design. Tests of the A/D converter will be presented.The multi-event buffer purpose is to de-randomize the even data in order to reduce the transmission speed. Preliminary tests of the first prototype will be presented.The board placed at the end of the ladders performs various functions. It reduces the amount of data through various cascaded algorithms with variable parameters and transmits the data to the SIU board. It also controls the test and slow control system for the ladder circuitry. Tests of the FPGA-based prototypes will be presented.Special care has been taken for the test problem. The ASICs designed are provided of a test control port based on teh IEEE 1149.1 JTAG standard. The same protocol is used for downloading configuration information
