Presentation at Quark Matter '99, Torino, Italy, 10-15 May 1999The Silicon Drift Detectors (SDDs) provide, through the measurement of the drift time of the charge deposited by the particle which crosses the detector, information on the impact point and on the energy deposition. The foreseen readout scheme is based on a single chip implementation of an integrated circuit that includes low-noise amplification, fast analog strorage and analog to digital conversion, thus avoiding the problems related to the analog signal transmission. A multi-event buffer that reduces the transmission bandwidth and a data compression/zero suppression unit complete the architecture.Abstract:In this paper, the system components design is described, together with the results of the first prototypes

Alberici, G

Bonazzola, G C

Bonvicini, V

Cavagnino, D

Cerello, P G

De Remigis, P

Falchieri, D

Gabrielli, A

Gandolfi, E

Giubellino, P

Hernández, R

Masetti, M

Mazza, G

Montaño-Zetina, L M

Nouais, D

Rashevsky, A

Rivetti, A

Tosello, F

Vacchi, A

Werbrouck, A E

The silicon drift detectors (SDDs) provide, through the measurement of the drift time of the charge deposited by the particle which crosses the detector, information on the impact point and on the energy deposition. The foreseen readout scheme is based on a single chip implementation of an integrated circuit that includes low-noise amplification, fast analog storage and analog to digital conversion, thus avoiding the problems related to the analog signal transmission. A multi-event buffer that reduces the transmission bandwidth and a data compression/zero suppression unit complete the architecture. In this paper the system components design is described, together with the results of the first prototypes. (5 refs)

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The silicon drift detector readout scheme for the inner tracker system of the ALICE experiment

1The Silicon Drift Detector readout scheme for the Inner Tracker Systemof the ALICE experimentG. Mazzaafor the ALICE collaborationaINFN Sezione di Torino,Via P. Giuria 1, Torino, ItalyG. Alberici1, G.C. Bonazzola2, V. Bonvicini6, D. Cavagnino2, P. Cerello1P. De Remigis1, D.Falchieri5, A. Gabrielli5, E. Gandol5, P. Giubellino1, R. Hernandez1;7, M. Masetti5, G. Mazza1,L.M. Montano1, D. Nouais1, A. Rashevsky6, A. Rivetti3;4, F. Tosello1A. Vacchi6, A. Werbrouck21INFN sezione di Torino, Italy2Universita di Torino, Italy3Politecnico di Torino, Italy4CERN Geneve, Switzerland5INFN sezione di Bologna, Italy6INFN sezione di Trieste, Italy7ICTP Trieste, ItalyThe Silicon Drift Detectors ( SDDs ) provide, through the measurement of the drift time of thecharge deposited by the particle which crosses the detector, information on the impact point andon the energy deposition. The foreseen readout scheme is based on a single chip implementationof an integrated circuit that includes low-noise amplication, fast analog storage and analog todigital conversion, thus avoiding the problems related to the analog signal transmission. A multi-event buer that reduces the transmission bandwidth and a data compression/zero suppressionunit complete the architecture.In this paper the system components design is described, together with the results of the rstprototypes.1. Introduction and requirementsThe silicon drift detectors are expected to provide high detection eciency over thewhole detector surface, a spatial precision of the order of 30 m, a two{track separationdown to O(600) m. In addition the detector should provide a charge resolution such thatthe dE/dx resolution is dominated by Landau uctuations, which the truncated mean ofthe four ITS dE/dx samples is around 10 % for M.I.P.A M.I.P. releases about 4 fC in the SDD. For hits far from the anode pads the chargecollected by one is typically one-third to one-half of the 4 fC; thus the tails of the hitsignal, essential for the position determination, will consist of less than 1 fC. The rangeof useful signals is limited between the noise level ( 250 e ) and 28-32 fC, but highersignals ( up to 160 fC ) are possible.The charge generated by a particle crossing the detector, depending on the crossingpoint and therefore on the drift time, can be collected by one anode as a fast gaussiansignal (  = 5 ns ) or by several anodes ( up to ve ) as a slower gaussian signal (  = 30ns ), due to the diusion during the charge drift through the detector.2In order to obtain the required precision the signal has to be sampled at quite highfrequency ( around 40 MHz ); the dynamic range is 10 bits while an 8 bit resolution issucient if a non linear readout is adopted.Due to the high sensitivity of the SDD to temperature variations and the very strin-gent requirement on the material budget which does not allow a very massive coolingsystem, the allowed power consumption for the electronic readout is very low ( below 5mW=channel ).2. System architectureIn order to minimize the power consumption, the signals coming from the detector arenot immediatly digitalized after the low noise preamplier. Instead, they are continuouslystored into an analog memory; only when the trigger signal is received the memory contentis frozen and the data are converted and sent to a digital event buer. In this way themost power demanding components work for a reduced pecentage of the time ( below10% ) greatly reducing the power consumption.After a local digital storage, which de-randomizes data for a lower transmission speed,the data have to be transferred to the acquisition system. Since the amount of data isvery large ( around 32.5 MBytes=event ) and more than 95% of these data are zero, adata reduction is performed. In order to minimize information losses an Human encoderhas been used, togheter with tunable lter functions which allow to reach the requiredcompression factor in the presence of noise. Figure 1 shows the full readout architecture.3. The front-end moduleIn the Inner Tracking System of the ALICE experiment the SDDs are placed on linearsupport structures called ladders. The front-end modules are placed on the ladders, nearthe detectors, and are based on two functional modules, named PASCAL and AMBRAarchitectures.The PASCAL architectureThe PASCAL architecture performs the low noise preamplication, analog storage andA/D conversion. A fully CMOS, low noise transimpedance amplier continuously writethe SDD signals into a switched capacitor analog memory at 40 MHz. When the triggersignal is received, the memory cells contents are converted in digital through a chargeredistribution successive approximation A/D converter.Current prototypes of the PASCAL architecture are designed as separate ASICs instandard technologies ( 0.7-0.8 m ); the A/D prototype fulls the specications whilethe preamplier, which has been succesfully tested in beam tests, has to be improvedin term of dynamic range. Promising results has been obtained also with the analogmemory. The nal goal is to design the full architecture as a single chip using the newdeep submicron technologies ( 0.25-0.35 m ).3End ladder moduleFront−end moduleSDD detectorsPASCALAMBRACARLOSSIUTest and slow control...Figure 1. The SDD ladder readout architectureThe AMBRA architectureIn order to decrease the number of transmission wires from the detectors to the endladder to a manageable number an event buer strategy has been adopted. The eventsare temporarly stored in local digital buers near the detectors; in this way the analogmemory can restart the write mode faster thus reducing the dead time. It has been shown[1] that with only two event buer the dead time due to event buer overow is around0.1%. The current prototype of the AMBRA architecture is a single ASIC designed in0.35 m technology4. The end ladder moduleThe end ladder modules are placed at both ends of the ladders, and contains thecompression circuit, the optical interface to the data acquisition system and the controlsystem.The most important functional module is the CARLOS architecture. Its purpose is to4compress the signals coming from the front-end readout units to a size compatible withthe requirements by the ALICE data acquisition system.Data compressionThe amount of data generated by the SDDs is 32.5 MBytes=event. Most of these dataare zeroes, therefore a data compression is required in order to save space on tape. Sincea simple zero suppression leads to an unacceptable information loss, several compressionalgorithms have been studied : Zero sequence encoding : sequences of zeroes are transmitted as a zero code followedby the number of consecutive zeroes. Since the occupancy is quite low, long zerosequences are highly probable. Simple threshold zero suppression : the data below a certain threshold, which takesinto account noise and pedestal, are set to zero. This technique is very easy toimplement and increases the number of zeroes by cutting non zero values due to thenoise. Unfortunately this results in information loss. Dierential encoding : instead of the samples, the dierence between consecutivesamples is transmitted. In this way any channel baseline value is translated into azero sequence. On the other hand a dierential encoding scheme is more sensitiveon sample errors during transmission. Simple threshold tolerance : it is a simple threshold zero suppression applied afterthe dierential encoding. It reduces the noise variations over a baseline, at theexpense of information loss. Human encoding : since the probability of lower codes is much higher than thehigher ones, using a variable length encoding leads to a losslessdata reduction. This reduction depends on the sample statistics; the implementa-tions is quite heavy in terms of hardware requirements. Multithreshold zero suppression : a sample is set to zero depending on its value andon the value of neighbour samples. In this way the information loss can be greatlyreduced with respect to single threshold zero suppression.An FPGA-based prototype of the rst 5 algorithms, with software tunable parameters,has been realized and is currently under test with the data taken from the ALICE SDDbeam tests [4]. The sixth algorithm is currently under evaluation. A detailed descriptionof this alghoritm can be found in [5].REFERENCES1. ALICE Technical Design Report, CERN/LHCC 99-122. ALICE Technical Proposal, CERN/LHCC 95-713. G. Mazza et al., CERN-LHCC-98-364. V.Bonvincini et al.,, ALICE/98-24 Internal note/SIL5. D.Cavagnino et al., ALICE/99-28 Internal note/SIL.

The Silicon Drift Detector readout scheme for the Inner Tracking System of the ALICE Experiment

The Silicon Drift Detector readout scheme for the Inner Tracking System of the ALICE Experiment

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