Quasi-static scheduling of independent tasks for reactive systems

The synthesis of a reactive system generates a set of concurrent tasks coordinated by an operating system. This paper presents a synthesis approach for reactive systems that aims at minimizing the overhead introduced by the operating system and the interaction among the concurrent tasks. A formal model based on Petri nets is used to synthesize the tasks. A practical application is illustrated by means of a real-life industrial example.Peer ReviewedPostprint (author's final draft

A BMC-Formulation for the Scheduling Problem in Highly Constrained Hardware Systems

Abstract This paper describes a novel application for SAT-based Bounded Model Checking (BMC) within hardware scheduling problems. First of all, it introduces a new model for control-dependent systems. In this model, alternative executions (producing "tree-like" scheduling traces) are managed as concurrent systems, where alternative behaviors are followed in parallel. This enables standard BMC techniques, producing solutions made up of single paths connecting initial and terminal states. Secondly, it discusses the main problem arising from the above choice, i.e., rewriting resource bounds, so that they take into account the artificial concurrencies introduced for controlled behaviors. Thirdly, we exploit SAT-based Bounded Model Checking as a verification technique mostly oriented to bug hunting and counter-example extraction. In order to consider resource constraints, the solutions of modifying the SAT solver or adding extra clauses are both taken into consideration. Preliminary experimental results, comparing our SAT based approach to state-of-the art BDD-based techniques are eventually presented

_ Synthesis of Embedded Software Using Free-Choice Petri Nets

Software synthesis from a concurrent functional specification is a key problem in the design of embedded systems. A concurrent specification is well-suited for medium-grained partitioning. However, in order to be implemented in software, concurrent tasks need to be scheduled on a shared resource (the processor). The choice of the scheduling policy mainly depends on the specification of the system. For pure dataflow specifications, it is possible to apply a fully static scheduling technique, while for algorithms containing data-dependent control structures, like the if-then-else or while-do constructs, the dynamic behaviour of the system cannot be completely predicted at compile time and some scheduling decisions are to be made at run-time. For such applications we propose a Quasi-static scheduling (QSS) algorithm that generates a schedule in which run-time decisions are made only for data-dependent control structures. We use Free Choice Petri Nets (FCPNs), as underlying model, and define quasi-static schedulability for FCPNs. The proposed algorithm is complete, in that it can solve QSS for any FCPN that is quasi-statically schedulable. Finally, we show how to synthesize from a quasi-static schedule a C code implementation that consists of a set of concurrent tasks

Single-photon generation from a nitrogen impurity center in GaAs

We have demonstrated single-photon emission from a nitrogen luminescence center in GaAs. An inhomogeneously broadened luminescence band formed by localized centers was observed in the spectral range from 1480 meV to 1510 meV at 5 K in nitrogen delta-doped GaAs. Optical properties of the individual centers were investigated by steady-state and time-resolved micro photoluminescence. We have found that a bright luminescence center emits single photons with a radiative lifetime of 650 ps, which is much shorter than the lifetime of NN pairs in previous reports

Architectural exploration of embedded systems

ERATO 湊離散構造処理系プロジェクト春のワークショップ（キックオフシンポジウム）. 2010年5月28日（金）～29日（土）. ERATO湊プロジェクト研究室

Generation of Minimal Size Code for Schedule Graphs

This paper proposes a procedure for minimizing the code size of sequential programs for reactive systems. It identifies repeated code segments (a generalization of basic blocks to directed rooted trees) and finds a minimal covering of the input control flow graphs with code segments. The segments are disjunct, i.e. no two segments have the same code in common. The program is minimal in the sense that the number of code segments is minimum under the property of disjunction for the given control flow specification. The procedur

Automatic trace analysis for logic of constraints

Verification of system designs continues to be a major chal-lenge today. Simulation remains the primary tool for mak-ing sure that implementations perform as they should. We present algorithms to automatically generate trace checkers from formulas written in the formal quantitative constraint language, Logic Of Constraints (LOC), to analyze the simu-lation traces for functional and performance constraint vio-lations. For many interesting formulas, the checkers exhibit linear time complexity and constant memory usage. We il-lustrate the usefulness and efficiency of this approach with large designs and traces