A methodology for sizing backup fuel-cell/battery hybrid power systems

Hybridization of fuel cells and batteries combines the advantages of both power sources. This paper proposes the use of fuel-cell/battery hybrid power systems as backup power systems and develops a methodology for sizing both fuel cell and battery bank, according to a minimum lifecycle cost criterion, from any defined hourly load profile and any defined backup time. For this purpose, an existing power-system-sizing computer tool has been used, but its initial capabilities have been extended. The developed methodology allows decisions to be taken before any investment is made. As a practical application, the methodology is used for the sizing of a backup power system for a telecommunication system

Monte Carlo Analysis of the Dynamic Behavior of InAlAs/InGaAs Velocity Modulation Transistors: A Geometrical Optimization

The influence of the geometry on the dynamic behavior of InAlAs/InGaAs velocity modulation transistors is analyzed by means of a Monte Carlo simulator in order to optimize the performance of this new type of transistor. In velocity modulation transistors, based on the topology of a double-gate high electron mobility transistor, the source and drain electrodes are connected by two channels with different mobilities, and electrons are transferred between both of them by changing the gate voltages in differential mode. Consequently, the drain current is modulated while keeping the total carrier density constant, thus in principle avoiding capacitance charging/discharging delays. However, the low values taken by the transconductance, as well as the high capacitance between the two gates in differential-mode operation, lead to a deficient dynamic performance. This behavior can be geometrically optimized by increasing the mobility difference between the two channels, by increasing the channel width and, mainly, by reducing the gate length, with a higher immunity to short channel effects than the traditional architectures.ROOTHz (FP7-243845

Kink effect and noise performance in isolated-gate InAs/AlSb High Electron Mobility Transistors

Kink effect can spoil the otherwise excellent low-noise performance of InAs/AlSb HEMTs. It has its origin in the pile up of holes (generated by impact ionization) taking place mainly at the drain side of the buffer, which leads to a reduction of the gate-induced channel depletion and results in a drain current enhancement. Our results indicate that the generation of holes by impact ionization and their further recombination lead to fluctuations in the charge of the hole pile up, which provoke an important increase of the drain-current noise, even when the kink effect is hardly perceptible in the output characteristics.ROOTHz (FP7-243845

Monte Carlo study of kink effect in Isolated-Gate InAs/AlSb High Electron Mobility Transistors

A semiclassical 2D ensemble Monte Carlo simulator is used to perform a physical microscopic analysis of kink effect in InAs/AlSb High Electron Mobility Transistors (HEMTs). Due to the small bandgap of InAs, these devices are very susceptible to suffer impact ionization processes, with the subsequent hole transport through the structure, both implicated in the kink effect. The results indicate that, for high enough VDS, holes generated by impact ionization tend to pile up in the buffer (at the gate-drain side) due to the valence-band energy barrier between the buffer and the channel. Due to this accumulation of positive charge the channel is further opened and ID increases, leading to the kink effect in the I-V characteristics and even to the device breakdown. The microscopic understanding of this phenomenon provides useful information for a design optimization of kink-effect-free InAs HEMTs.ROOTHz (FP7-243845

Monte Carlo model for the analysis and development of III-V Tunnel-FETs and Impact Ionization-MOSFETs

Impact-ionization metal-oxide-semiconductor FETs (I-MOSFETs) are in competition with tunnel FETs (TFETs) in order to achieve the best behaviour for low power logic circuits. Concretely, III-V I-MOSFETs are being explored as promising devices due to the proper reliability, since the impact ionization events happen away from the gate oxide, and the high cutoff frequency, due to high electron mobility. To facilitate the design process from the physical point of view, a Monte Carlo (MC) model which includes both impact ionization and band-to-band tunnel is presented. Two ungated InGaAs and InAlAs/InGaAs 100 nm PIN diodes have been simulated. In both devices, the tunnel processes are more frequent than impact ionizations, so that they are found to be appropriate for TFET structures and not for I-MOSFETs. According to our simulations, other narrow bandgap candidates for the III-V heterostructure, such as InAs or GaSb, and/or PININ structures must be considered for a correct I-MOSFET design

Monte Carlo Analysis of Impact Ionization in Isolated-Gate InAs/AlSb High Electron Mobility Transistors

We perform a physical analysis of the kink effect in InAs/AlSb high electron mobility transistors by means of a semiclassical 2D ensemble Monte Carlo simulator. Due to the small bandgap of InAs, InAs/AlSb high electron mobility transistors are very susceptible to suffer from impact ionization processes, with the subsequent hole transport through the structure, both implicated in the kink effect. When the drain-to-source voltage VDS is high enough for the onset of impact ionization, holes generated tend to pile up at the gate-drain side of the buffer. This occurs due to the valence-band energy barrier between the buffer and the channel. Because of this accumulation of positive charge, the channel is further opened and the drain current ID increases, leading to the kink effect in the I–V characteristics.ROOTHz (FP7-243845

Analysis of Surface Charge Effects and Edge Fringing Capacitance in Planar GaAs and GaN Schottky Barrier Diodes

[EN]In this article, by means of a 2-D ensemble Monte Carlo simulator, the Schottky barrier diodes (SBDs) with realistic geometries based on GaAs and GaN are studied as promising devices for increasing the high-frequency performance- and power-handling capability of frequency mixers and multipliers. The nonlinearity of the capacitance–voltage (C–V) characteristic is the most important parameter for optimizing the performance of SBDs as frequencymultipliers. The small size of the diodes used for ultrahigh-frequency applications makes the value of its intrinsic capacitance to deviate from the ideal one due to fringing effects. We have observed that the value of the edge capacitancewell into reverse bias does not depend on the applied voltage. We define an edge-effect parameter beta, which, interestingly, is affected by the presence or absence of surface charges at the semiconductor–dielectric interface, sigma . Two physical models have been considered: a fixed sigma related to a surface potential Vs constant surface-charge model (CCM) and a self-consistent model in which the local value of sigma is dynamically evaluated depending on the surrounding electron density self-consistent surface-charge model (SCCM). Using the CCM, we obtain that beta depends on the depth of the depletion region Ws created by the surface charges, nearly irrespectively of the epilayer doping or semiconductor type. The more realistic SCCM indicates that, at low frequencies, when the surface charges are able to follow the variations of the applied voltage, the value of beta approaches the one obtained without surface charges,while the high-frequency value (the significant one) is smaller.Spanish MINECO and FEDER under Project TEC2017-83910-R and Junta de Castilla y León and FEDER under Project SA254P18

Time-domain Monte Carlo simulation of GaN planar Gunn nanodiodes in resonant circuits

In this work we present a theoretical study based on time-domain Monte Carlo (MC) simulations of GaN-based Self-Switching Diodes (SSDs) oriented to the experimental achievement and control of the sub-THz Gunn-oscillations potentially provided by these devices. With this aim, an analysis of the frequency performance of SSDs connected to a resonant RLC parallel circuit, is reported here. V-shaped SSDs have been found to be more efficient, in terms of the DC to AC conversion efficiency η, than similar square-shape ones. Indeed, a value of η of at least 0.80%, can be achieved with appropriate RLC elements, even when considering heating effects. When the influence of parasitic elements such as the crosstalk capacitance Ctalk is evaluated, MC simulations have shown that the resonant circuit must contain a capacitance C higher than Ctalk in order to obtain experimentally useful values of η. This condition can be reached by integrating a sufficiently high number N of parallel SSDs in the fabricated devices. MC simulations have also shown that when several diodes are fabricated in parallel the oscillations of all the SSDs are not synchronized, but this problem is solved by the attachment of a resonant RLC tank