Resource Efficient Hardware Architecture for Fast Computation of Running Max/Min Filters

Running max/min filters on rectangular kernels are widely used in many digital signal and image processing applications. Filtering with a k×k kernel requires of k2−1 comparisons per sample for a direct implementation; thus, performance scales expensively with the kernel size k. Faster computations can be achieved by kernel decomposition and using constant time one-dimensional algorithms on custom hardware. This paper presents a hardware architecture for real-time computation of running max/min filters based on the van Herk/Gil-Werman (HGW) algorithm. The proposed architecture design uses less computation and memory resources than previously reported architectures when targeted to Field Programmable Gate Array (FPGA) devices. Implementation results show that the architecture is able to compute max/min filters, on 1024×1024 images with up to 255×255 kernels, in around 8.4 milliseconds, 120 frames per second, at a clock frequency of 250 MHz. The implementation is highly scalable for the kernel size with good performance/area tradeoff suitable for embedded applications. The applicability of the architecture is shown for local adaptive image thresholding

Block-synchronous Harmonic Control for Scalable Trajectory Planning

ISBN : 978-953-7619-20-6Trajectory planning consists in finding a way to get from a starting position to a goal position while avoiding obstacles within a given environment or navigation space. Harmonic functions may be used as potential fields for trajectory planning. Such functions do not have local extrema, so that control algorithms may reduce to locally descend the potential field until reaching a minimum, when obstacles correspond to maxima of the potential and goals correspond to minima. This chapter presents a parallel hardware implementation of this navigation method on reconfigurable digital circuits. Trajectories are estimated after the iterated computation of the harmonic function, given the goal and obstacle positions of the navigation problem. The proposed massively distributed implementation locally computes the direction to choose to get to the goal position at any point of the environment. Changes in this environment may be immediately taken into account, for example when obstacles are discovered during an on-line exploration. To fit real-world applications, our implementation has been designed to deal with very large navigation environments while optimizing computation time

Fault Tolerance of Self Organizing Maps

International audienceBio-inspired computing principles are considered as a source of promising paradigms for fault-tolerant computation. Among bio-inspired approaches , neural networks are potentially capable of absorbing some degrees of vulnerability based on their natural properties. This calls for attention, since beyond energy, the growing number of defects in physical substrates is now a major constraint that affects the design of computing devices. However, studies have shown that most neural networks cannot be considered intrinsically fault tolerant without a proper design. In this paper, the fault tolerance of Self Organizing Maps (SOMs) is investigated, considering implementations targeted onto field programmable gate arrays (FPGAs), where the bit-flip fault model is employed to inject faults in registers. Quantization and distortion measures are used to evaluate performance on synthetic datasets under different fault ratios. Three passive techniques intended to enhance fault tolerance of SOMs during training/learning are also considered in the evaluation. We also evaluate the influence of technological choices on fault tolerance: sequential or parallel implementation, weight storage policies. Experimental results are analyzed through the evolution of neural prototypes during learning and fault injection. We show that SOMs benefit from an already desirable property: graceful degradation. Moreover, depending on some technological choices, SOMs may become very fault tolerant, and their fault tolerance even improves when weights are stored in an individualized way in the implementation

A spatio-temporal approach to individual mobility modeling in on-device cognitive computing platforms

The increased availability of GPS-enabled devices makes possible to collect location data for mining purposes and to develop mobility-based services (MBS). For most of the MBSs, determining interesting locations and frequent Points of Interest (POIs) is of paramount importance to study the semantic of places visited by an individual and the mobility patterns as a spatio-temporal phenomenon. In this paper, we propose a novel approach that uses mobility-based services for on-device and individual-centered mobility understanding. Unlike existing approaches that use crowd data for cloud-assisted POI extraction, the proposed solution autonomously detects POIs and mobility events to incrementally construct a cognitive map (spatio-temporal model) of individual mobility suitable to constrained mobile platforms. In particular, we focus on detecting POIs and enter-exits events as the key to derive statistical properties for characterizing the dynamics of an individual’s mobility. We show that the proposed spatio-temporal map effectively extracts core features from the user-POI interaction that are relevant for analytics such as mobility prediction. We also demonstrate how the obtained spatio-temporal model can be exploited to assess the relevance of daily mobility routines. This novel cognitive and on-line mobility modeling contributes toward the distributed intelligence of IoT connected devices without strongly compromising energy

Fault Tolerance of Self Organizing Maps

International audienceAs the quest for performance confronts resource constraints, major breakthroughs in computing efficiency are expected to benefit from unconventional approaches and new models of computation such as brain-inspired computing. Beyond energy, the growing number of defects in physical substrates is becoming another major constraint that affects the design of computing devices and systems. Neural computing principles remain elusive, yet they are considered as the source of a promising paradigm to achieve fault-tolerant computation. Since the quest for fault tolerance can be translated into scalable and reliable computing systems, hardware design itself and the potential use of faulty circuits have motivated further the investigation on neural networks, which are potentially capable of absorbing some degrees of vulnerability based on their natural properties. In this paper, the fault tolerance properties of Self Organizing Maps (SOMs) are investigated. To asses the intrinsic fault tolerance and considering a general fully parallel digital implementations of SOM, we use the bit-flip fault model to inject faults in registers holding SOM weights. The distortion measure is used to evaluate performance on synthetic datasets and under different fault ratios. Additionally, we evaluate three passive techniques intended to enhance fault tolerance of SOM during training/learning under different scenarios

Low-cost hardware implementations for discrete-time spiking neural networks

In this paper, both GPU (Graphing Processing Unit) based and FPGA (Field Programmable Gate Array) based hardware implementations for a discrete-time spiking neuron model are presented. This generalized model is highly adapted for large scale neural network implementations, since its dynamics are entirely represented by a spike train (binary code). This means that at microscopic scale the membrane potentials have a one-to-one correspondence with the spike train, in the asymptotic dynamics. This model also permit us to reproduce complex spiking dynamics such as those obtained with general Integrate-and-Fire (gIF) models. The FPGA design has been coded in Handel-C and VHDL and has been based on a fixed-point reconfigurable architecture, while the GPU spiking neuron kernel has been coded using C++ and CUDA. Numerical verifications are provided

Embedded harmonic control for trajectory planning in large environments

International audienceThis paper presents an embedded FPGA­based architecture to compute navigation trajectories along a harmonic potential. The goals and obstacles may be changed during computation. Large environments are split into blocks. This approach, together with the use of an increasing precision, enables an optimization of the overall computation time that is theoretically and experimentally studied. Implementation results confirm outstanding speedup factors

Stochastic and Asynchronous Spiking Dynamic Neural Fields

International audienceBio-inspired neural computation attracts a lot of attention as a possible solution for the future challenges in designing computational resources. Dynamic neural fields (DNF) provide cortically inspired models of neural populations to which computation can be applied for a wide variety of tasks, such as perception and sensorimotor control. DNFs are often derived from continuous neural field theory (CNFT). In spite of the parallel structure and regularity of CNFT models, few studies of hardware implementations have been carried out targeting embedded real-time processing. In this article, a hardware-friendly model adapted from the CNFT is introduced, namely the RSDNF model (randomly spiking dynamic neural fields). Thanks to their simplified 2D structure, RSDNFs achieve scalable parallel implementations on digital hardware while maintaining the behavioral properties of CNFT models. Spike-based computations within neurons in the field are introduced to reduce interneuron connection bandwidth. Additionally, local stochastic spike propagation ensures inhibition and excitation broadcast without a fully connected network. The behavioral soundness and robustness of the model in the presence of noise and distracters is fully validated through software and hardware. A field programmable gate array (FPGA) implementation shows how the RSDNF model ensures a level of density and scalability out of reach for previous hardware implementations of dynamic neural field models

Using context-awareness for storage services in edge computing

Modern mobile networks face a dynamic environment with massive devices and heterogeneous service expectations that will need to significantly scale for 5G. Edge computing approaches aim at enhancing scalability through strategies like computation offloading and local storage services, which will be fundamental to deploying large-scale distributed applications. Unlike the cloud, edge resources are limited, which call for novel techniques to handle large volumes of up- and downstream data under a changing environment. Being closer to data consumers and producers, a compelling view is to adopt context-aware techniques for enabling the edge to work with patterns from mobile traffic at different spatiotemporal scales. In this article, we overview the challenges and opportunities of edge storage from the perspective of context-awareness. We introduce a conceptual architecture to learn and exploit context information for enhancing uplink and downlink scenarios. Finally, we outline future directions for edge applications