Modeling of Wearout, Leakage, and Breakdown of Gate Dielectrics

Abstract We present a set of models for the simulation of gate dielectric wearout, leakage, and breakdown. Wearout is caused by the leakage-induced creation of neutral defects at random positions in the dielectric layer, which, if occupied, degrade the threshold voltage of the device. Leakage is due to direct and trap-assisted tunneling through these defects. Finally, gate dielectric breakdown is triggered by the formation of a conductive path through the insulator. To allow the trap characterization and for the simulation of fast transients the modeling of trap charging and decharging processes is outlined. The model has been implemented into a threedimensional device simulator and is used for the characterization of ZrO 2 -based dielectrics and for the study of gate leakage and wearout effects in standard CMOS inverter circuits

Emerging memory technologies: trends, challenges, and modeling methods”,

a b s t r a c t In this paper we analyze the possibility of creating a universal non-volatile memory in a near future. Unlike DRAM and flash memories a new universal memory should not require electric charge storing, but alternative principles of information storage. For the successful application a new universal memory must also exhibit low operating voltages, low power consumption, high operation speed, long retention time, high endurance, and a simple structure. Several alternative principles of information storage are reviewed. We discuss different memory technologies based on these principles, highlight the most promising candidates for future universal memory, make an overview of the current state-of-the-art of these technologies, and outline future trends and possible challenges by modeling the switching process

Stochastic Model of the Resistive Switching Mechanism in Bipolar Resistive Random Access Memory: Monte Carlo Simulations”,

Memory is an indispensible important component of any modern integrated circuit. While MOSFET scaling has reached tremendous advances, semiconductor memory scaling is lagging behind. Standard DRAM cell scaling is hampered by the presence of a capacitor which is difficult to reduce in size. Z-RAM uses a bitcell composed of a single transistor without a capacitor (1T/0C) ("Z" stands for Zero capacitor), unlike traditional one transistor plus one capacitor (1T/1C) DRAM bitcells. The advanced Z-RAM bitcells built on a multiple-gate MOSFET (MuGFET), where the parasitic bipolar transistor [1] is utilized, which exists in SOI MOSFETs. The current flows through the body of the structure and is thus much increased. The majority carriers generated due to impact ionization are stored under the gates. The stored charge offers a good control over the current. The threshold voltage is modified by the stored charge guaranteeing two states of the bipolar transistor with high and low current, correspondingly. The stored charge for the two states is shown in Charge-based memories including flash are, however, gradually approaching the physical limits of scalability, and the search for new nonvolatile memory concepts has significantly accelerated. Several new memory structures as potential substitutes of the flash memory were invented and developed: a technology of phase change RAM (PCRAM), spin transfer torque RAM (STTRAM), carbon nanotube RAM (NRAM), copper bridge RAM (CBRAM), racetrack memory, and resistive RAM (RRAM). A new type of nonvolatile memory must exhibit low operating voltages, low power consumption, high operation speed, long retention time, high endurance, simple structure, and small size. One of the most promising candidates for future universal memory is the resistive random access memory (RRAM) The spin transfer torque random access memory (STTRAM) is another promising candidate for future universal memory. The reduction of the current density required for switching and the increase of the switching speed are among the most important challenges in this area. A decrease in the critical current density for the penta-layer magnetic tunnel junction was reported i

Stress evolution in the metal layers of TSVs with Bosch scallops

a b s t r a c t We have studied the stress evolution in the tungsten film of a particular open TSV technology during the thermal processing cycle. The film is attached to the via's wall, where scallops were observed as a result of the Bosch processing. Our work describes a scheme which considers the scallops on the TSV and conjugates a stress model for thin-films with the traditional mechanical FEM approach. The results reveal potential reliability issues and a specific evolution of the stress in the tungsten layer

Transport Properties of Spin Field-Effect Transistors Built on Si and InAs

Abstract We investigate the properties of ballistic spin fieldeffect transistors (SpinFETs). First we show that the amplitude of the tunneling magnetoresistance oscillations decreases dramatically with increasing temperature in SpinFETs with the semiconductor channel made of InAs. We also demonstrate that the [100] orientation of the silicon fin is preferred for practical realizations of silicon SpinFETs due to stronger modulation of the conductance as a function of spin-orbit interaction and magnetic field

Heatring - Smart Investigation of Temperature Impact On Integrated Circuit Devices

To investigate the electrical on-chip-transistor behavior at different temperatures usually the transistor area on the wafer is heated by external heat sources to operate at a specific temperature. To avoid using external heat sources a heatring structure was developed which directly controls the temperature of the investigated transistor area on the wafer, guaranteeing very fast warming up and cooling off duration times. Testing the heatring functionality was performed by electro-thermal simulations, the results of which were verified by measurements. Keywords : heatring, electro-thermal simulatio

Mathematical models as research data via flexiformal theory graphs

Mathematical modeling and simulation (MMS) has now been established as an essential part of the scientific work in many disciplines. It is common to categorize the involved numerical data and to some extent the corresponding scientific software as research data. But both have their origin in mathematical models, therefore any holistic approach to research data in MMS should cover all three aspects: data, software, and models. While the problems of classifying, archiving and making accessible are largely solved for data and first frameworks and systems are emerging for software, the question of how to deal with mathematical models is completely open. In this paper we propose a solution -- to cover all aspects of mathematical models: the underlying mathematical knowledge, the equations, boundary conditions, numeric approximations, and documents in a flexi\-formal framework, which has enough structure to support the various uses of models in scientific and technology workflows. Concretely we propose to use the OMDoc/MMT framework to formalize mathematical models and show the adequacy of this approach by modeling a simple, but non-trivial model: van Roosbroeck's drift-diffusion model for one-dimensional devices. This formalization -- and future extensions -- allows us to support the modeler by e.g. flexibly composing models, visualizing Model Pathway Diagrams, and annotating model equations in documents as induced from the formalized documents by flattening. This directly solves some of the problems in treating MMS as "research data'' and opens the way towards more MKM services for models

The Core Human Microbiome: Does It Exist and How Can We Find It? A Critical Review of the Concept

The core microbiome, which refers to a set of consistent microbial features across populations, is of major interest in microbiome research and has been addressed by numerous studies. Understanding the core microbiome can help identify elements that lead to dysbiosis, and lead to treatments for microbiome-related health states. However, defining the core microbiome is a complex task at several levels. In this review, we consider the current state of core human microbiome research. We consider the knowledge that has been gained, the factors limiting our ability to achieve a reliable description of the core human microbiome, and the fields most likely to improve that ability. DNA sequencing technologies and the methods for analyzing metagenomics and amplicon data will most likely facilitate higher accuracy and resolution in describing the microbiome. However, more effort should be invested in characterizing the microbiome’s interactions with its human host, including the immune system and nutrition. Other components of this holobiontic system should also be emphasized, such as fungi, protists, lower eukaryotes, viruses, and phages. Most importantly, a collaborative effort of experts in microbiology, nutrition, immunology, medicine, systems biology, bioinformatics, and machine learning is probably required to identify the traits of the core human microbiome

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

The scaling of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 50 V) requires a subsequent optimisation of SJ unit. The scaling and the SJ optimisation are carried out with physically based commercial TCAD device simulations by Silvaco. The study is based on a meticulous calibration of drift-diffusion simulations against experimental characteristics of a 1 μm gate length SJ multi-gate MOSFET (SJ-MGFET) aiming at improving density, switching speed, drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate scaling of the device architecture to improve the device performance by optimising doping profile to achieve an avalanche-enabled device under a charge balanced condition. The optimised SJ-MGFETs scaled by a factor of 0.5 and 0.25, with a folded alternating U-shaped n/p-SJ drift region pillar of a width of 0.3 μm and a trench depth of 2.7 μm, achieve a low specific on-resistance (Ron,sp) of 7.68 mΩ⋅mm2 and 2.24 mΩ⋅mm2 (VGS = 10 V) and BV of 48 V and 26 V, respectively. The scaled 0.5 μm and 0.25 μm gate length SJ-MGFETs offer a transconductance (gm) of 20 mS/mm and 56 mS/mm at a drain voltage of 0.1 V, respectively, greatly improving the levels of integration in a CMOS architecture