Review of real brain-controlled wheelchairs

This paper presents a review of the state of the art regarding wheelchairs driven by a brain-computer interface (BCI). Using a brain-controlled wheelchair (BCW), disabled users could handle a wheelchair through their brain activity, granting autonomy to move through an experimental environment. A classification is established, based on the characteristics of the BCW, such as the type of electroencephalographic (EEG) signal used, the navigation system employed by the wheelchair, the task for the participants, or the metrics used to evaluate the performance. Furthermore, these factors are compared according to the type of signal used, in order to clarify the differences among them. Finally, the trend of current research in this field is discussed, as well as the challenges that should be solved in the future

Brain switch mode: an alternative to drive a brain-controlled wheelchair

To date, different control paradigms of low level navigation have been tested for brain-controlled wheelchairs, mainly divided into continuous or discrete control [1]. However, these paradigms have certain drawbacks such as the need to keep the mental tasks active for a long time, as in continuous mode, or the impossibility to freely choose any distance of the movement or the turn, as in the discrete mode. An alternative paradigm to solve these problems could be the use of the brain switch mode [2], which would allow a more flexible control of the distance, requiring a lower workload for the user.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

Proposals of Control Paradigms Applied to a Brain-Controlled Wheelchair

Proposals of Control Paradigms Applied to a Brain-Controlled Wheelchair, Ron-Angevin R., Velasco-Álvarez F., Fernández Rodriguez A., Proceeding og the BITs 4th Annual World Congress of Smart Material 2018, Osaka (Japan), 6-8 March 2018Several of the neurological diseases that human beings can result in severe disabilities. In some cases, people who suffer from such deficiencies lose any chance of communication with their environment, being the only possible alternative to give the brain a new channel not based on muscular activity, allowing these people to send messages and commands to the external world. The systems that allows the latter is what is known as Brain-Computer Interfaces (BCI). Their common feature is to process the brain’s electrical activity for extracting information that can be used to command an external device, as for example, a wheelchair to provide them some mobility. One of the most important limitations of these brain controlled wheelchair is to guarantee that a person can, through his mental activity, safely control the variety of navigation commands that provide control of the wheelchair: advance, turn, move back, and stop. The vast majority of the mobile robot navigation applications that are controlled via a BCI demand that the user performs as many different mental tasks as there are different control commands, worsening the classification accuracy. In order to enable an effective and autonomous wheelchair navigation with a BCI system without worsening user performance, the Brain–Computer Interface (BCI) group of the University of Málaga (UMA-BCI) proposed and later developed a new paradigm based on the discrimination of only two classes (one active mental task versus any other mental activity), which enabled the selection of four commands: move forwards, turn right, move backward and turn left. The final aim of this contribution is to show how to control a robotic wheelchair through the use of only two mental tasks. The mapping of these two mental tasks into several navigation commands allows the Brain-Controlled Wheelchair to be moved and turned in order to achieve effective navigation.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

Experimental Evidence of Power Efficiency due to Architecture in Cellular Processor Array Chips

Speeding up algorithm execution can be achieved by increasing the number of processing cores working in parallel. Of course, this speedup is limited by the degree to which the algorithm can be parallelized. Equivalently, by lowering the operating frequency of the elementary processors, the algorithm can be realized in the same amount of time but with measurable power savings. An additional result of parallelization is that using a larger number of processors results in a more efficient implementation in terms of GOPS/W. We have found experimental evidence for this in the study of massively parallel array processors, mainly dedicated to image processing. Their distributed architecture reduces the energy overhead dedicated to data handling, thus resulting in a power efficient implementationMinisterio de Economía y Competitividad TEC2015-66878-C3-1-RCentro para el Desarrollo Tecnológico e Industrial IPC- 20111009Junta de Andalucía TIC 2338-2013Office of Naval Research (USA) N00014141035

Experimental Evidence of Power Efficiency due to Architecture in Cellular Processor Array Chips

Speeding up algorithm execution can be achieved by increasing the number of processing cores working in parallel. Of course, this speedup is limited by the degree to which the algorithm can be parallelized. Equivalently, by lowering the operating frequency of the elementary processors, the algorithm can be realized in the same amount of time but with measurable power savings. An additional result of parallelization is that using a larger number of processors results in a more efficient implementation in terms of GOPS/W. We have found experimental evidence for this in the study of massively parallel array processors, mainly dedicated to image processing. Their distributed architecture reduces the energy overhead dedicated to data handling, thus resulting in a power efficient implementationMinisterio de Economía y Competitividad TEC2015-66878-C3-1-RCentro para el Desarrollo Tecnológico e Industrial IPC- 20111009Junta de Andalucía TIC 2338-2013Office of Naval Research (USA) N00014141035

Optimum Selection of DNN Model and Framework for Edge Inference

This paper describes a methodology to select the optimum combination of deep neuralnetwork and software framework for visual inference on embedded systems. As a first step, benchmarkingis required. In particular, we have benchmarked six popular network models running on four deep learningframeworks implemented on a low-cost embedded platform. Three key performance metrics have beenmeasured and compared with the resulting 24 combinations: accuracy, throughput, and power consumption.Then, application-level specifications come into play. We propose a figure of merit enabling the evaluationof each network/framework pair in terms of relative importance of the aforementioned metrics for a targetedapplication. We prove through numerical analysis and meaningful graphical representations that only areduced subset of the combinations must actually be considered for real deployment. Our approach can beextended to other networks, frameworks, and performance parameters, thus supporting system-level designdecisions in the ever-changing ecosystem of embedded deep learning technology.Ministerio de Economía y Competitividad (TEC2015-66878-C3-1-R)Junta de Andalucía (TIC 2338-2013)European Union Horizon 2020 (Grant 765866

Early forest fire detection by vision-enabled wireless sensor networks

Wireless sensor networks constitute a powerful technology particularly suitable for environmental monitoring. With regard to wildfires, they enable low-cost fine-grained surveillance of hazardous locations like wildland-urban interfaces. This paper presents work developed during the last 4 years targeting a vision-enabled wireless sensor network node for the reliable, early on-site detection of forest fires. The tasks carried out ranged from devising a robust vision algorithm for smoke detection to the design and physical implementation of a power-efficient smart imager tailored to the characteristics of such an algorithm. By integrating this smart imager with a commercial wireless platform, we endowed the resulting system with vision capabilities and radio communication. Numerous tests were arranged in different natural scenarios in order to progressively tune all the parameters involved in the autonomous operation of this prototype node. The last test carried out, involving the prescribed burning of a 95 x 20-m shrub plot, confirmed the high degree of reliability of our approach in terms of both successful early detection and a very low false-alarm rate. Journal compilationMinisterio de Ciencia e Innovación TEC2009-11812, IPT-2011-1625-430000Office of Naval Research (USA) N000141110312Centro para el Desarrollo Tecnológico e Industrial IPC-2011100

Concurrent focal-plane generation of compressed samples fromtime-encoded pixel values

Compressive sampling allows wrapping the relevant content of an image in a reduced set of data. It exploits the sparsity of natural images. This principle can be employed to deliver images over a network under a restricted data rate and still receive enough meaningful information. An efficient implementation of this principle lies in the generation of the compressed samples right at the imager. Otherwise, i. e. digitizing the complete image and then composing the compressed samples in the digital plane, the required memory and processing resources can seriously compromise the budget of an autonomous camera node. In this paper we present the design of a pixel architecture that encodes light intensity into time, followed by a global strategy to pseudo-randomly combine pixel values and generate, on-chip and on-line, the compressed samples.Ministerio de Economía y Competitividad TEC 2015-66878-C3-1-RJunta de Andalucía TIC 2338-2013Office of Naval Research (USA) N000141410355CONACYT (Mexico) MZO-2017-29106

Robust symmetric multiplication for programmable analog VLSI array processing

This paper presents an electrically programmable analog multiplier. The circuit performs the multiplication between an input variable and an electrically selectable scaling factor. The multiplier is divided in several blocks: a linearized transconductor, binary weighted current mirrors and a differential to single-ended current adder. This paper shows the advantages introduced using a linearized OTA-based multiplier. The circuit presented renders higher linearity and symmetry in the output current than a previously reported single-transistor multiplier. Its inclusion in an array processor based on CNN allows for a more accurate implementation of the processing model and a more robust weight distribution scheme than those found in previous designs.Office of Naval Research (USA) N-00014- 02-1-0884Ministerio de Ciencia y Tecnología TIC2003-09817-C02-0

Propuesta para mejorar la competitividad de la cadena de distribución del sector fresero en Cundinamarca

Administrador (a) de EmpresasPregrad