A large dynamic range radiation-tolerant analog memory in a quarter- micron CMOS technology

An analog memory prototype containing 8*128 cells has been designed in a commercial quarter-micron CMOS process. The aim of this work is to investigate the possibility of designing large dynamic range mixed-mode switched capacitor circuits for high-energy physics (HEP) applications in deep submicron CMOS technologies. Special layout techniques have been used to make the circuit radiation tolerant. The memory cells employ gate-oxide capacitors for storage, permitting a very high density. A voltage write-voltage read architecture has been chosen to minimize the sensitivity to absolute capacitor values. The measured input voltage range is 2.3 V (the power supply voltage V/sub DD/ is equal to 2.5 V), with a linearity of almost 8 bits over 2 V. The dynamic range is more than 11 bits. The pedestal variation is +or-0.5 mV peak-to-peak. The noise measured, which is dominated by the noise of the measurement setup, is around 0.8 mV rms. The characteristics of the memory have been measured before irradiation and after 100 kGy (SiO/sub 2/), and they do not degrade after irradiation. (15 refs)

"CMAD", a Full Custom ASIC, for the Upgrade of COMPASS RICH-1

An 8 channel, full-custom ASIC prototype, named ”CMAD”, designed for the readout of the RICH-I detector system of the COMPASS experiment at CERN is presented. The task of the chip is amplifying the signals coming from fast multi-anode photomultipliers and comparing them against a threshold adjustable on-chip on a channel by channel basis. CMAD, developed using a 350nm commercial CMOS technology, occupies an area of 4.7x3.2mm2 and consumes 26mW/Ch power from a 3.3 V single source

Epitaxial hybrid pixel with triggerless readout in 130nm Cmos technology for the Micro Vertex Detector of the Panda experiment

The Micro Vertex Detector (MVD) is the innermost one of the Panda experiment, sitting around the beam pipe. The sensors are arranged in a barrel section with two pixel and two strip layers, and 6 forward disks with mixed pixel and microstrip sensors. For the pixel detector part, a hybrid solution with thinned epitaxial sensors was chosen. The main requirements for the readout include: a pixel size of 100 · 100 μm2, an input charge measurement with 12 b that implies an amplitude resolution of 1 part out of 4096, a working frequency of 155.5MHz, and a triggerless acquisition. The readout of the pixel detector is based on a front end chip, named Topix, that is under development. The Asic will provide the time position with a resolution of 6.43 ns and a charge measurement with a Time Over Threshold (TOT) technique; it features a matrix of 116 · 110 pixel cell channels and 311 Mb/s serializers as output ports. A 130nm Cmos technology has been used to reduce the circuit size and to provide tolerance for the total dose, besides techniques against single event upset have been implemented. A Topix prototype with the full cell has been completely tested for radiation damage before and after irradiation, and a new release has been submitted to build an hybrid assembly. The stringent requirements in terms of space for the MVD lead to an architecture based on optical links. The GigaBit Transceiver (GBT) from CERN has been chosen as the baseline solution for the interface to the data acquisition. Low mass cables based on aluminium on polyimide are under development for the interconnections

Test results of the front-end system for the Silicon Drift Detectors of ALICE

The front-end system of the Silicon Drift Detectors (SDDs) of the ALICE experiment is made of two ASICs. The first chip performs the preamplification, temporary analogue storage and analogue-to-digital conversion of the detector signals. The second chip is a digital buffer that allows for a significant reduction of the connection from the front-end module to the outside world. In this paper, the results achieved on the first complete prototype of the front-end system for the SDDs of ALICE are presented

Front end electronics for pixel detector of the PANDA MVD

ToPix 2.0 is a prototype in a CMOS 0.13 ¹m technology of the front-end chip for the hybrid pixel sensors that will equip the Micro-Vertex Detector of the PANDA experiment at GSI. The Time over Threshold (ToT) approach has been employed to provide a high charge dynamic range (up to 100 fC) with a low power dissipation (15 ¹W/cell). In an area of 100¹m£100¹m each cell incorporates the analog and digital electronics necessary to amplify the detector signal and to digitize the time and charge information. The ASIC includes 320 pixel readout cells organized in four columns and a simplified version of the end of column readout

Relation of study quality, concordance, take home message, funding, and impact in studies of influenza vaccines: systematic review

Objective To explore the relation between study concordance, take home message, funding, and dissemination of comparative studies assessing the effects of influenza vaccines

Beam test results of the irradiated Silicon Drift Detector for ALICE

The Silicon Drift Detectors will equip two of the six cylindrical layers of high precision position sensitive detectors in the ITS of the ALICE experiment at LHC. In this paper we report the beam test results of a SDD irradiated with 1 GeV electrons. The aim of this test was to verify the radiation tolerance of the device under an electron fluence equivalent to twice particle fluence expected during 10 years of ALICE operation.Comment: 6 pages,6 figures, to appear in the proceedings of International Workshop In high Multiplicity Environments (TIME'05), 3-7 October 2005, Zurich,Switzerlan

A 5 Gb/s Radiation Tolerant Laser Driver

A laser driver for data transmission at 5 Gb/s has been developed as a part of the Giga Bit Transceiver (GBT) project. The Giga Bit Laser Driver (GBLD) targets High Energy Physics (HEP) applications for which radiation tolerance is mandatory. The GBLD ASIC can drive both VCSELs and some types of edge emitting lasers. It is essentially composed of two drivers capable of sinking up to 12 mA each from the load at a maximum data rate of 5 Gb/s, and of a current sink for the laser bias current. The laser driver include also pre-emphasis and duty cycle control capabilities