The front-end system of the Silicon Drift Detectors (SDDs) of the ALICE experiment is made of two ASICs. The first chip performs the preamplification, temporary analogue storage and analogue-to-digital conversion of the detector signals. The second chip is a digital buffer that allows for a significant reduction of the connection from the front-end module to the outside world. In this paper, the results achieved on the first complete prototype of the front-end system for the SDDs of ALICE are presented

Anelli, G

Martínez, M I

Mazza, G

Rivetti, A

Rotondo, F

Tosello, F

Wheadon, R

CERN Document Server

AbstractThe front−end system of the Silicon Drift Detectors(SDDs) of the ALICE experiment is made of two ASICs. Thefirst chip performs the preamplification, temporary analoguestorage and analogue−to−digital conversion of the detectorsignals. The second chip is a digital buffer that allows for asignificant reduction of the connections from the front−endmodule to the outside world. In this paper the results achieved on the first completeprototype of the front−end system for the SDDs of ALICEare presented.I. IntroductionSilicon drift detectors provide xy coordinates of thecrossing particles with a spatial precision of the order of 30µm, as well as a charge resolution such that the dE/dx isdominated by Landau fluctuation. The detector is hexagon−shaped with a total area of 72.5x87.6 mm2 and an active areaof 70.2x75.3 mm2. It is divided into two 35 mm drift regions.At the end of each drift region 256 anodes collect the charge.The pitch of the anodes is 294 µm.[1][2]Each anode has to be readout with a sampling frequencyof 40 MS/s. The number of samples to be taken per eventmust cover the whole drift time, which is around 6 µs,therefore a number of 256 samples has been chosen. Thetotal amount of data for each half−detector (corresponding toone drift region) is 64 kSamples.The basic idea behind our readout scheme is to convertthe samples into a digital format as soon as possible. Due tothe tight requirements in term of material and also the smallspace available on the support structures ( ladders ) it wouldbe extremely difficult to transmit analogue data outside thedetectors at the required speed.Owing to the low power budget ( 5 mW/channel ) it isnot possible to have a 40 MS/s A/D converter for eachchannel, therefore a different approach has been adopted.The signal from the detector is continuously amplified andsampled on an 256−cells analogue memory at 40 MS/s.When the trigger signal is received the analogue memorystops the write phase and moves to the read phase where itssamples are converted by a slower A/D converter. This ofcourse introduces some dead time since during theconversion the system is not sampling the detector signal.The maximum allowed dead time is 1 ms/event. Areasonable value for the settling time of the analoguememory is 500 ns and a 2 MS/s ADC every two channels isalso acceptable in term of area and power consumption. Withthose values the dead time is 512 µs, a factor of two belowthe requirement.A schematic view of the readout architecture is shown inFigure 1.In order to further decrease the number of cables from thefront end system a digital multi−event buffer is placed closeto the front−end chip. The data from the A/D converter arefirst quickly stored into a digital event buffer over a wide busand then sent outside the detector area over a single 8−bitbus for each front−end board. The introduction of the event buffers introduces anadditional dead time; however, it has been calculated thatwith 4 buffers the dead time due to event buffer overflow isonly 0.04%. Test results of the front−end system for the silicon drift detectors of ALICEG.Mazza1, A.Rivetti2, G.Anelli3, M.I.Martinez1,4, F.Rotondo1, F.Tosello1, R.Wheadon1for the ALICE Collaboration1 INFN Sezione di Torino, via P.Giuria 1 10125 Torino, Italy2 Dip. di Fisica Sperimentale dell’Universita‘ di Torino, via P.Giuria 1 10125 Torino, Italy3 CERN, 1211 Geneva 23, Switzerland4 CINVESTAV, Mexico City, Mexicomazza@to.infn.itrivetti@to.infn.itFigure 1 : SDD readout scheme...Silicon Drift DetectorsFront−end boards End ladder boardLow voltage boardsAMBRAPASCALCARLOSGOLlaserDCSVoltage regulators& LVDS tx/rxII. The front−end ASICsThe front−end system is based on two ASICs, namedPASCAL and AMBRA.PASCAL can be divided in three parts : 64preamplification and fast analogue storage channels, 32successive approximation A/D converters (each ADC isshared between two analogue memory channels) and a logiccontrol unit that provides the basic control signals for theanalogue memory and the  converter. The present prototype is half sized : 32 input channelswith preamplifier and 256 cells analogue memory areconnected to 16 A/D converters. A scheme of the prototypeis shown in Figure 2.The preamplifier is based on the standard chargeamplifier plus shaper configuration and provides a gain ofaround 35 mV/fC with a peaking time of 40 ns. Thepreamplifier is DC coupled with the detector; baselinevariations and detector leakage currents are compensated viaa low frequency feedback around the second stage. Theamplifier is buffered with a class−AB output stage in order tobe able to drive the analogue memory with a low powerconsumption.[3]The analogue memory is an array of 256x32 switchedcapacitor cells controlled via a shift register. The cells can bewritten at 40 MHz and read out at 2 MHz. The architecture issuch that the voltage across the capacitor (and not thecharge) is written and read; therefore the sensitivity to theabsolute value of the capacitors and to the timing is greatlyreduced.[5]The 10−bit A/D converter is based on the successiveapproximation principle; a scaled array of switchedcapacitors provides both the DAC and the subtractionfunctions, and a three−stage offset compensated comparatoris used to check if the switched capacitor array output ispositive or negative and to drive the successiveapproximation register that, in turn, controls the DAC. Thesuccessive approximation architecture is a good compromisebetween speed and low power consumption; it requires nooperational amplifiers and only one zero crossingcomparator. The conversion speed is one clock cycle perbit.[6]Two calibration lines, connected to the even and oddchannel inputs via a 180 fF capacitor, provide the capabilityof testing the circuit without the detector.The prototype has been designed in a commercial 0.25µm CMOS technology with radiation tolerant layouttechniques. The chip size is 7x6 mm2.AMBRA provides 4 level of event buffering. Each bufferhas a size of 16 kbytes and is based on static RAM in order toincrease the SEU resistance and to avoid the refreshcircuitry. The control unit provides buffer management,controls the operations of PASCAL and provides the front−end interface to the rest of the system. The present prototypehas only 2 event buffers and can work up to 50 MHz. [4]The prototype has been designed in Alcatel 0.35 µmtechnology with standard layout. The chip size is 4.4x3.8mm2. 89% of the core area is occupied by the two memorybuffers.The PASCAL−AMBRA system operates as follows :when AMBRA receveis the trigger signal it sends an SoP(Start of oPeration) command to PASCAL. PASCAL stopsthe sampling of the detector outputs and starts the readout ofthe analogue memory and the A/D conversion. When the firstsample of the 32 channels has been converted, a write_req(write request) signal is sent to AMBRA which in turn, if abuffer is available, replies with a write_ack (writeacknowledge ) and starts the data acquisition. The sequencecontinues for the other samples of the analogue memory untilAMBRA sends an EoP (End of oPeration ) command, thenPASCAL returns to the acquisition phase. The EoPcommand can be issued for two reasons : all the 256 cellshave been readout, or an abort signal has been received. Thelatter indicates that the trigger signal, which is generatedfrom the level−0 ALICE trigger, has not been confirmed bythe higher level triggers. Since the reject probability can bevery high (it can reach 99.8% in Pb−Pb interactions) it isvery important to stop as soon as possible the conversion andrestart the acquisition.As soon as an event buffer is full, AMBRA starts thetransmission of the data. The data_write command is used toindicate that there are valid data on the output bus. Thissignal remains high as long as the data are transmitted. Adata_end signal remains high for one clock cycle incorrespondance of the last byte. It is possible to suspend thedata transmission via the data_stop command.Figure 3 : AMBRA schemeEvent BufferAEvent BufferBControl UnitWrite Unit Read UnitWrite Counter Read Counterdata_inwrite_reqwrite_ackdata_outdata_writedata_stoptrig_busytrig_abortFigure 2 : PASCAL schemeAnalogue memorySAR FFSAR FFSAR FFMUXControl UnitPreamplifier + bufferA/D converterIII. Test results of the front−end circuitThe two prototypes have been evaluated together on atest board. The inputs have been provided via the calibration lineswhile the outputs have been readout via a logic stateanalyzer. A data pattern generator has been used to providethe clock and the other digital control signals to the twochips. The two prototypes have also been tested connected to adetector in a test beam at CERN PS. Data analysis is in apreliminary stage; therefore in this paper we discuss only thelab measurement performed on the system.Figure 4 shows a typical output from a 4 fC charge signalfrom the calibration lines. Even with a δ−like pulse at least 4samples are significantly above the noise in the timedirection. For a particle crossing the detector far from theanodes a slower signal is obtained and more samples can beabove the noise floor; on the other hand, since the totalcharge does not change, the signal to noise ratio on theindividual sample is worse.Figure 5 shows the output code against the input chargefor the 32 channels of a chip. It can be seen that the dynamicrange is  well above the required 32  fC. Figure 6 shows the deviation of the curve of Figure 5from linear fit. The non−linearity is less than 0.8% over thewhole dynamic range and it is mainly related to thesaturation of the preamplifier at the highest part of the range.Another source of non−linearity is the voltage dependance ofthe memory capacitors, again in the highest part of the range.Figure 7 shows the gain variation across channels of 5different chips. The number of tested chip is too small tohave a significant statistic; however, from these results thevariation between channels of the same chip is of the orderof few percent while the chip to chip variation is of the orderof 10−15%.A small slope of the gain distribution across the channelsof the same chip can be identified. This slope is due to avoltage drop on the power and reference lines across thechip. With a proper sizing of these critical lines it will beprobably possible to recover some of the gain variation in thefinal version of the chip.Noise measurements give an rms noise below 2 counts,which corresponds to around 400 e−. This number is slightlyabove the requirements and comes essentially from thecoupling between the analogue part and the digital one at thesubstrate level and/or at the board level ( the measured noiseof the preamplifier alone is less that 180 e− ). A bettergrounding scheme is under study for the final version of thechip and for the final board design.The measurements give less than 5 and around 10 mW perchannel for average and peak power consumption,Figure 6 : Linearity0 5 10 15 20 25 30−20−1001020Deviation from linear fitFigure 7 : Gain0 3 5 8 10 13 15 18 20 23 25 28 3020.021.022.023.024.025.026.027.028.029.030.0Gain ( counts/fC )chip 0chip 1chip 3chip 4chip 5Figure 5 : Dynamic range0 3 5 8 10 13 15 18 20 23 25 28 30 330100200300400500600700800900Output code vs. input chargech 0ch 1ch 2ch 3ch 4ch 5ch 6ch 7ch 8ch 9ch 10ch 11ch 12ch 13ch 14ch 15ch 16ch 17ch 18ch 19ch 20ch 21ch 22ch 23ch 24ch 25ch 26ch 27ch 28ch 29ch 30ch 31Figure 4 : Typical output from a 4 fC input signal0501001500 10 20 30 40 50 60Cell numberADC countsrespectively. These numbers fulfill the ALICE SDDrequirements.Another important aspect is the amplifier recovery timefrom saturation. In the ALICE environment very high signals(up to 400 fC) are possible. Despite these signals are not ofconcern for the data analysis, it is important that thepreamplifier does not remain "hanged" for milliseconds.Tests show a recovery time of 350 ns for a 100 fC signal.This time rises with higher signals and saturates at 500 ns forsignals above 200 fC. These very high signals are very rare,therefore this recovery time is acceptable.IV. Radiation tolerance and technology issuesThe drift detectors and the front−end electronics in theALICE environment will have to survive to a quite low, butnot negligible, level of radiation. The foreseen dose for 10years of operation is around 20 krds. This value is at the limitof what a modern standard technology can accept, thereforethe choice between a standard and a radiation hardtechnology was not straightforward.While radiation hard technologies remain two or threegeneration behind the standard technologies, a new approachbased on specific layout techniques and deep submicronstandard technologies has been carried out by the RD49research program at CERN. The effectivness of this approachhas been demostrated up to 30 Mrds. Its main disadvantage issome area penalty, expecially in the digital design, ifcompared with a standard deep submicron technology.However, the digital radiation tolerant cells are still smallerwhen compared with the standard cells of a radiation hardprocesses.Owing to the low radiation level in ALICE the firstPASCAL prototype has been designed in a commercial 0.25µm with radiation tolerant techniques while the first AMBRAhas been designed in Alcatel 0.35 µm technology with thecommercial standard cell library. The reason of this choice was that, on one side, analoguecircuits are more sensitive to leakage currents and thresholdvariation (expecially the analogue memory, where leakagecurrents would destroy the cells content ) while, on the otherhand, digital circuits are more robust but the area penalty dueto the radiation tolerant techniques is much more significant.Radiation tests for total dose effects have shown verysmall variations in the parameters of the PASCAL chip up to30 Mrds. The irradiated AMBRA chips show fullfunctionality up to 1 Mrd; unfortunately the leakage currentshows a dramatic increase at 50−60 krds ( Figure 8 ) and,despite this effect does not affect the chip functionality, itwill lead to an unacceptable power consumption.For this and other reasons (cost, phasing out of the 0.35µm process by Alcatel ) the final version of the AMBRA chipwill use the 0.25 µm technology radiation tolerant standardcells library.V. ConclusionsA 32 channels prototype and a 2 event−buffer prototypeof the two ASICs for the readout of the ALICE SDDs havebeen designed and tested. The 2−chip system shows anexcellent linearity and a good gain uniformity. The systemfulfills the ALICE requirements and shows the effectivnessof the chosen architecture.A minor problem related to voltage drop in the internalpower supply and reference lines has been identified and willbe corrected in the final version. Owing to the fact that thethreshold for the leakage current in the 0.35 µm process usedfor AMBRA is too close to the foreseen radiation level, thefinal version of both chips will be designed using theradiation tolerant approach.VI. References[1] ALICE Technical Design Report, CERN/LHCC 99−12[2] ALICE Technical Proposal, CERN/LHCC 95−71[3] A.Rivetti et al, "A mixed−signal ASIC for the silicondrift detectors of the ALICE experiment in a 0.25 µmCMOS" CERN−2000−010, CERN−LHCC−2000−041, pp.142−146[4] G.Mazza et al, "Test Results of the ALICE SDDElectronic Readout Prototypes", CERN−2000−010, CERN−LHCC−2000−041, pp. 147−151, [5] G.Anelli et al., "A Large Dynamic Range Radiation−Tolerant Analog Memory in a Quarter−Micron CMOSTechnology", IEEE Trans. on Nucl. Sci., vol.48, pp. 435−439, Jun 2001 [6] A.Rivetti et al., "A Low−Power 10 bit ADC in a 0.25µm CMOS: Design Consideration and Test Results",presented at Nucl. Sc. Symposium and Med. ImagingConference, Lyon, Oct 2000Figure 8 : AMBRA irradiation test results : supply current(mA) vs dose (krds)0 25 50 75 100 125 150 175 200 225 250 275 300 3250255075100125150175200Supply current  vs dose 

Test results of the front-end system for the Silicon Drift Detectors of ALICE

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