Idzik, M

Mazza, G

Rivetti, A

Rotondo, F

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AbstractThis paper describes building blocks designed for thereadout and detector control systems of the Silicon DriftDetectors (SDDs) of ALICE. In particular, the paperfocuses on a low−dropout regulator, a charge redistributionADC and a current steering DAC. All the parts have beendeveloped in a commercial 0.25µm CMOS technology, usingradiation tolerant layout practices.I. INTRODUCTIONSilicon Drift Detectors will be used in the third and fourthlayer of the Inner Tracking System of the ALICE experiment[1]. The specifications and the implementation of theelectronics for the SDDs are described in detail in [2], [3],[4] and will not be covered here. For the purpose of this workit is sufficient to remember that the SDD system requires thedevelopment of four full−custom ASICs, which are used bothfor data processing and control tasks. Two of these chips arepurely digital and two are mixed−mode designs. Thebuilding blocks presented in this paper will be integrated inthe mixed−mode circuits.The more complex mixed−signal component is thefront−end chip (named PASCAL), which performs theamplification, filtering and analogue−to−digital conversionof the detector signals. In its final implementation, the ASIChost 64 amplifiers, each coupled with a row of a switchedcapacitor array (SCA), having 256 cells. When a triggersignal is received, 32 on board ADCs convert the analoguedata stored in the pipeline to a 10 bit digital code. A singleADC digitises the content of two adjacent rows of the SCA.The converter, described in detail in [5], is based on thesuccessive approximation technique [6], which offers a verygood trade−off between speed and power consumption. Dueto the severe space constraints on the front−end board, thereference voltage for the ADCs must be provided on chip.The generation of this reference is an issue, because thevoltage source will be heavily loaded by the ADCs, whichoperate in parallel. For these reasons, a dedicate low dropoutregulator had to be developed. The design of this block aswell as the first results of the experimental measurements arediscussed in section II.The chip for the Detector Control System (DCS)performs the monitoring of vital parameters of the systemand the control of some critical voltages and currents. Forinstance, this chip is used to measure the temperature of theelectronics board. Additionally, it has to generate theamplitude−controlled signal which is needed to trigger thecalibration circuitry of the detector. Therefore, an ADC anda DAC are the basic elements of the DCS ASIC. Thesecircuits need to provide a medium resolution (8 bits), whileminimising area and power consumption. They aredescribed in section III and in section IV of this paper,respectively.II. THE LOW DROPOUT REGULATORThe low dropout regulator provides a stable DC voltageof 1.9V that is needed by the ADCs of the front−end chip.Depicted in fig. 1, the circuit uses a linear scheme, [7]whose key elements are the error amplifier A1, the passtransistor P0 and the resistive feedback network formed by R1and R2. All these components are integrated on chip. Theoutput voltage is derived from the reference voltage VBG,provided by a bandgap circuit.The capacitor C0 serves to filter the current spikes andprovides the frequency compensation of the loop. Given thehigh value required for C0 (1µF), an external discretecomponent must be used. In fact, it is very important toassure that the regulator works in all conditions with anadequate phase margin. The value chosen for C0 guaranteesthat the feedback loop has always a phase margin of 76degrees.   Figure 1 : LDO simplified scheme.New building blocks for the ALICE SDD readout and detector control system in acommercial 0.25µm CMOS technologyA.Rivetti, G. Mazza, M. Idzik and F. Rotondofor the ALICE collaborationINFN, Sezione di Torino, Via Pietro Giuria 1 − 10125 Torino −Italyrivetti@to.infn.itThe LDO can deliver to the load a maximum current of100mA. The static power consumption of the circuit is2.5mW and it occupies an area of 230 x 150 µm2 (excludingthe bandgap reference, which will be shared by severalcircuits on the front−end chip.)In order to check the functionality of the device before itsintegration in the final version of the front−end ASIC, adedicated test chip has been produced and measured. The testresults show a good agreement with the computersimulations. The circuit provides the required referencevoltage with an overall accuracy of 1%. As an example ofthe performance of the circuit, Figure 2 reports the plotobtained for the load regulation. The current driven by theload is changed from zero to the maximum value of 100mA.The maximum change in the output voltage is 13 mV,resulting in a load regulation figure (defined as ∆V0/∆I0) of0.13 Ω. Figure 2 : LDO load regulation performanceThe line regulation has been checked for Vdd rangingfrom 2.2 to 2.7 V, corresponding to the maximum powersupply variation acceptable for the front−end chip. In thisinterval, the output voltage changes by 1mV giving a lineregulation (∆V0/∆Vi) of 0.002. The measured noise at theoutput of the LDO is 250µV rms, but the accuracy of thismeasurement is limited by the experimental set−up.III. THE ANALOGUE TO DIGITAL CONVERTERThe ADC is an evolution of the converter embedded inthe front−end chip. In order to profit as much as possiblefrom existing blocks, the same successive approximationtopology used in PASCAL has been chosen. The mainmodification occurs in the DAC, in which the resolution hasbeen traded for area. Figure 3 shows the block diagram of atypical implementation of a 8 bit charge redistribution ADC.The two basic elements of the circuit are a voltagecomparator and a DAC made of binary weighted capacitors. The conversion is performed in two steps: In the acquisition phase, all the capacitors areconnected in parallel and are used to sample the inputsignal. In the redistribution phase, the capacitors are usedindividually to generate binary fractions of thereference voltage, which are compared with the samplepreviously stored. Figure 3 : Schematic of a generic 8 bit ADCThe conversion algorithm is described in detail in [6]. Forthe purpose of our discussion, it is sufficient to observe thatif the DAC is implemented exactly with the scheme ofFigure 3, its area doubles for every extra bit of resolutionrequired. For instance, an 8 bit DAC occupies twice the areaneeded by a 7 bit  one.In order to reduce the surface of the DAC, the scheme ofFigure 4 has been used. In this approach, the DAC has beensplitted in two blocks, each with a 5 bit capability.       Figure 4 : Schematic of the implemented ADC withsegmented DACThe first DAC samples also the input signal and iscapacitively coupled to the second DAC, which is used onlyduring the redistribution phase.In this way, two advantages are achieved: The total area is equivalent to the area of a 6 bit DAC,which is four times smaller than the area of a direct 8 bitDAC. Since the sampling is performed only by the main DAC,the input capacitance of the ADC is reduced by a factoreight with respect a straightforward 8 bit design.The matching between the capacitors is critical to obtaina good linearity in the ADC. To improve the matching, inthe layout only a fundamental cell is used and the biggercapacitors are built by connecting a suitable number ofelementary cells in parallel. Actually, the structure of Figure                                         VREFVREFVIN  C  C   2C       4C   8C       16C     32C     64C  128CGNDVREFOUTVREFVREF16C4C2CC                                  GNDC8C  VINVREF                                  8CGND16C4C2CC          VREF        O UT VREFC    0 500 1000 1500 2000 2500 30001.9051.9071.9101.9121.9151.9171.920Load regulationtime (ns)Voltage (V)4 is more sensitive than the architecture of Figure 3 to theeffect of random mismatches. This point can be understoodby noting that in the ADC of Figure 4 the capacitor whichdetermines the MSB is formed by 16 unit elements, whereasin Figure 3 it is composed by 128 individual cells. In thelatter case, the MSB capacitor will be more precise, becauseit uses more elements in parallel and the random erroraffecting each one tend to average out. For this reason, theADC is built using two 5 bit DACs instead of two 4 bitDACs, which in principle would be sufficient to get a total 8bit resolution.It must also be observed that the circuit of Figure 3 couldbe used to implement a 10 bit ADC. However, for thematching reasons mentioned above this resolution can not beassured if the individual capacitor is implemented with theminimum size allowed by the technology. In our applicationa 10 bit resolution is not required, whereas the area of thecircuit is important. Therefore, the minimum sizecapacitance has been used, targeting 8 bit performance.Nevertheless, two extra bits have been made available fortest purposes.The layout of the circuit has an area of 300 x 800 µm2 ,which is about 60% of what would be required by the directimplementation of Figure 3.A test chip containing three identical converters hasbeen designed and fabricated. The ADC is tested by sendingto the circuit a sinusoidal input signal and reading the digitaloutput codes with a logic state analyser. The data are theprocessed with a dedicated software to calculate the DNL,the INL, and the FFT. In the measurements, the ADC isoperated with a full scale range of 1V, which results in aLSB of 4mV.During the test, the circuit is running with a clock of40MHz. Since two clock cycles are left to sample the inputsignal and to compensate the offset in the comparator [5], 10clock periods are required for a complete 8 bit conversion.The sampling frequency is hence 4Msample/sec. The circuitis powered with a single rail power supply of 2.5V anddissipates 3mW.Figure 5 show the result of a typical FFT that is obtainedin the measurements.Figure 5 : FFT measured for the ADC.As it can be seen from the figure, the second harmonic iswell below 48dB and the  ADC has a very low distortion.The converter has a maximum DNL of 0.8 LSB, which issufficient to guarantee a 8 bit resolution without missingcodes. To give a more intuitive view of the performance ofthe circuit, Figure 6 shows the result of the conversion of afull scale ramp.Figure 6 : Digitization of a full scale ramp.IV. THE DIGITAL TO ANALOGUE CONVERTERThe 8 bit DAC is the other analogue building blocks forthe DCS chip. It must be observed that switched capacitorDAC used in the ADC is very compact, but it suffers from anumber of drawbacks. These drawbacks make it inadequateto work as a stand−alone component. For instance, theparasitic capacitance on the top plate attenuates the voltagesteps generated by the DAC. This and other phenomena areof minor concern in an ADC, since they affect in the sameway both the signal and the partitions of the referencevoltage that are used in the conversion. However, they candetermine severe limitations when the DAC is used just toconvert a digital code to an analogue level. For these reasonsit has been necessary to develop a new circuit, using adifferent approach.The circuit is based on a current steering configurationand is made of an array of current sources and a digitalcontrol logic. In order to improve as much as possible thematching between the sources and hence the linearity, a fullythermometric segmentation has been chosen. Therefore, theDAC is formed by 256 identical cells, which are organised ina 16x16 matrix.The schematic of the elementary bit cell is shown inFigure 7. The cell is essentially a cascode current mirror,which copies a reference current. The sizes of the transistorare dictated by the need of having an adequate area andoverdrive voltage, in order to get an appropriate matching. Ifthe cell is selected by the control logic, the switch driven bysel_b is closed and the current is directed towards the outputnode. At the output node, all the currents generated by theindividual mirrors are summed and converted to a voltage.The current−to−voltage conversion can be carried−out eitherby a simple resistor or by a transimpedance amplifier. Bothoptions are available in the DAC.Each elementary cell is biased with a tail current of 5µA,resulting in a static power consumption 3mW for the wholeanalogue part of the DAC. The circuit has been optimised to reach a conversionspeed of at least 50Msamples/sec.Figure 7 : Schematic of the unit cell of the DAC.Shown if Figure 7, the layout of the complete DAC hasan area of 1 x 0.6 mm2..  The test chip is in production and noexperimental result is available at the time of writing. Figure 8 : Layout  of the full DACV. CONCLUSIONSThe front−end and detector control electronics of theSDD of ALICE requires complex analogue building blocks.The most critical circuits have been prototyped, in order tocheck their functionality before their integration in the finalASICs. These circuits are a low dropout regulators, an ADCand a DAC with moderate resolution (8 bits) but reducedarea.The low dropout regulator is needed to generate on boardthe reference voltage for the ADC of the front−end chip. Thecircuit integrates all the critical parts except the filteringcapacitor and has shown characteristics which are adequatefor the application. The output voltage change by 1mV for achange of 0.5V in the power supply. The regulator is able toprovide a maximum current of 100mA with an outputvoltage drop of 13mV. The noise is less than 200µV rms.The analogue to digital converter uses a segmentedarchitecture in the DAC, in order to minimise the area asmuch as possible. The area of the ADC is 0.24mm2. Thecircuit has a resolution of 8 bits over a full scale range of 1Vand operate at a speed of 4Msamples/sec, dissipating 3mVfrom a 2.5V supply.The last building block that has been developed is acurrent steering digital to analogue converter. This circuit isstill in production and it will be tested in the forthcomingmonths.All the three designs discussed in this paper have beenimplemented in a 0.25µm CMOS technology, using enclosedlayout transistors and guardrings to prevent the damage fromionising radiation.VI. REFERENCES[1] The ALICE collaboration, "Technical proposal of theALICE experiment", CERN/LHCC 95−71, Dec. 1995.[2] The ALICE collaboration, "Technical design report ofthe Inner Tracking System", CERN/LHCC 99−12, June1999, pp 83−173.[3] A. Rivetti, G. Anelli, F. Anghinolfi, G. Mazza, P.Jarron, "A Mixed−Signal ASIC for the Silicon DriftDetectors of the ALICE Experiment in a 0.25µm CMOS",Proceedings of the Sixth Workshop on Electronics for LHCExperiments  CERN, LHCC/2000−041,  Oct. 2000.[4] G. Mazza et al., "Test Results of the Front−endSystem for the Silicon Drift Detectors of ALICE,Proceedings of the Seventh Workshop on Electronics forLHC Experiments, Stockholm, Sept. 2001.[5] A. Rivetti, G. Anelli, F. Anghinolfi, G. Mazza and F.Rotondo, "A Low−Poer 10 bit ADC in a 0.25µm CMOS:Design Considerations and Test Results", IEEE Transactionson Nuclear Science, Aug.  2001.[6] J. L. McCreary and P. Gray, "All−MOS ChargeRedistribution Analog−to−Digital Conversion Techniques −Part I", IEEE Journal of Solid State Circuits, vol. SC 10, no.6, pp. 371−379, Dec. 1975.[7] Texas Instruments, "Technical Review of lowDropout Regulator Operation and Performance" applicationnote SLVA072, Aug. 1999.

New building blocks for the ALICE SDD readout and Detector Control System in a commercial 0.25 $\mu$ m CMOS technology

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New building blocks for the ALICE SDD readout and Detector Control System in a commercial 0.25 μ\muμ m CMOS technology

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New building blocks for the ALICE SDD readout and Detector Control System in a commercial 0.25 $\mu$ m CMOS technology