Simulation and Modeling of Racetrack Memories With VCMA Synchronization

The control of the motion of magnetic domains is of crucial interest for the development of several spintronic applications, such as high-density racetrack memories and domain wall logic. In these devices, domain wall manipulation can be achieved via pulsed currents or applying external fields. However, real-world applications require accurate signal synchronization systems, keeping limited the power budget. Up to now, geometrical restrictions in the magnetic wire, known as notches, were used to confine domain walls at the expense of high resolution of the fabrication process. The solution based on the Voltage-Controlled Magnetic Anisotropy (VCMA) effect appears more promising--it is successful for controlling the skyrmion motion--avoids the need for strong depinning currents, simplifies the fabrication process, and gives more freedom in the control logic. The anisotropy variation induced by the VCMA can create barriers or wells that can be used to limit the movement of domain walls and obtain an effective synchronization. In this article, we propose a system-level evaluation of the effectiveness of the proposed VCMA synchronization method. Starting from a two-coordinates model, the motion of domain walls, the performance, and the efficiency of the approach are evaluated. We modeled the delay using SPICE. The VCMA showed clear advantages in the realization of the confinement structure at the system level with respect to the notch solution

Audio-Based Identification of Queen Bee Presence Inside Beehives

Honeybees are essential for the health of people and the planet. They play a key role in the pollination of most crops. The high mortality observed in the last decade, caused by stress factors among which the climate change, have raised the necessity of remote sensing the beehives to help monitor the health of honeybees and better understand this phenomenon. Several solutions have been proposed in the literature, and some of them include the analysis of in-hive sounds. In this scenario, we explore the potential of machine learning methods for queen bee detection using only the audio signal, being a good indicator of the colony state of health. In particular, we experiment support vector machines and neural network classifiers. We consider the effect of varying the audio chunk duration and the adoption of different hyperparameters

ToPoliNano: Nanoarchitectures Design Made Real

Many facts about emerging nanotechnologies are yet to be assessed. There are still major concerns, for instance, about maximum achievable device density, or about which architecture is best fit for a specific application. Growing complexity requires taking into account many aspects of technology, application and architecture at the same time. Researchers face problems that are not new per se, but are now subject to very different constraints, that need to be captured by design tools. Among the emerging nanotechnologies, two-dimensional nanowire based arrays represent promising nanostructures, especially for massively parallel computing architectures. Few attempts have been done, aimed at giving the possibility to explore architectural solutions, deriving information from extensive and reliable nanoarray characterization. Moreover, in the nanotechnology arena there is still not a clear winner, so it is important to be able to target different technologies, not to miss the next big thing. We present a tool, ToPoliNano, that enables such a multi-technological characterization in terms of logic behavior, power and timing performance, area and layout constraints, on the basis of specific technological and topological descriptions. This tool can aid the design process, beside providing a comprehensive simulation framework for DC and timing simulations, and detailed power analysis. Design and simulation results will be shown for nanoarray-based circuits. ToPoliNano is the first real design tool that tackles the top down design of a circuit based on emerging technologie

Parallel Computation in the Racetrack Memory

Racetrack memories are promising candidates for next-generation solid-state storage devices. Various racetrack memories have been proposed in the literature, skyrmion based or domain wall based. However, none of them show integrated computing capabilities. Here, we introduce a new domain wall based racetrack concept that can operate both as a memory and as a computing device. The computation is defined by changing locally the anisotropy of the film. Stray fields from nearby cells are exploited to implement reconfigurable logic gates. We demonstrate that the racetrack array can operate in parallel in every cell. This is achieved by an external out-of-plane Zeeman field applied to the array. As proof-of-principle, we verified the single computing cell and multiple connected cells operating in parallel by micromagnetic simulations. Logic NAND/NOR is implemented independently in every computing cell. This study provides the guidelines for the development and optimization of this family of logic gates

An Integrated Multi-Sensor System for Remote Bee Health Monitoring

Over 75% of the world's food crops depends on pollination and in particular by the inestimable value of the service provided by bees. Besides, the bee colony health is a good indicator of the quality of the environment and it is strongly affected by many aspects such as beekeepers' management practices, policies adopted for cropping and land use. However, the climate change, the intensive agriculture, pesticides, biodiversity loss, Varroa mites and pollution are the leading cause of bees death world wide. The role of beekeepers is of extremely importance to mitigate this damage. Apiaries are usually located in remote environment an require frequent visit by the beekeepers. Indeed, the beekeeping sector lacks of suitable tools for risk assessment and decision making that can be used by stakeholders. Smart monitoring systems assessing the health of the colony and the honey production would be beneficial for such community. In this work, we present a prototype of an embedded multi-sensor system for beehive monitoring with the aim of providing a simple solution to beekeepers. Indeed, the proposed system do not require modification of the beehive and it is compact enough to be simply inserted in the brood box. It measures the vital parameters of the beehive, such as temperature, weight, humidity and CO2 concentration. It exploits the low power communication protocol LoRaWAN for the data transmission. The collected data are made available to the beekeeper through a web application. We show the effectiveness of such compact, non-invasive embedded system with its installation in an apiary

Device for Data Storage and Processing, and Method Thereof

A device for data storage and processing includes: at least two input racetrack elements having a plurality of first magnetization regions; at least one output racetrack element having a plurality of second magnetization regions, wherein a magnetization vector is adapted to switch from a first direction to the opposite one, or vice versa, by way of a magnetic field of reduced intensity compared with a magnetic field required to produce a similar switching of a magnetization vector of the first magnetization region, wherein the input racetrack elements and output racetrack element are configured in such a way as to constitute at least one elementary logic gate, wherein at least two of the first magnetization regions are magnetically coupled to at least one of the second magnetization regions

A Unified Approach for Performance Degradation Analysis from Transistor to Gate Level

In this paper, we present an extensive analysis of the performance degradation in MOSFET based circuits. The physical effects that we consider are the random dopant fluctuation (RDF), the oxide thickness fluctuation (OTF) and the Hot-carrier-Instability (HCI). The work that we propose is based on two main key points: First, the performance degradation is studied considering BULK, Silicon-On-Insulator (SOI) and Double Gate (DG) MOSFET technologies. The analysis considers technology nodes from 45nm to 11nm. For the HCI effect we consider also the time-dependent evolution of the parameters of the circuit. Second, the analysis is performed from transistor level to gate level. Models are used to evaluate the variation of transistors key parameters, and how these variation affects performance at gate level as well.The work here presented was obtained using TAMTAMS Web, an open and publicly available framework for analysis of circuits based on transistors. The use of TAMTAMS Web greatly increases the value of this work, given that the analysis can be easily extended and improved in both complexity and depth

Virtual Clocking for NanoMagnet Logic

Among emerging technologies nanomagnet logic (NML) has recently received particular attention. NML uses magnets as constitutive elements, and this leads to logic circuits where there is no need of an external power supply to maintain their logic state. As a consequence, a system with intrinsic memory and zero stand-by power consumption can be envisioned. Despite the interesting nature of NML, a fundamental open problem still calls for a solution that could really boost the NML technology: the clock system. It constrains the layout of circuits and leads to a potentially high dynamic power consumption if not carefully conceived. The first clock system developed was based on the generation of a magnetic field through an on-chip current. After that other types of NML, based on several different types of clock systems, were proposed to improve clocking. We present here our proposal for a new clock delivery method. We named this system “virtual clock.” It offers several important advantages over previous solutions. First, it notably simplifies the clock generation network, reducing the complexity of the fabrication process. It improves the efficiency of circuits layout, substantially reducing interconnections overhead and boosting the reliability of the majority voter. It enables the fabrication of in-plane NML circuits with two layers, while they were confined to one single layer up to now. Finally, it allows to globally reduce dynamic power consumption by considerably shrinking circuits area. Overall the “virtual clock” system that we propose represents an important step forward in the development of the NML technology

Skyrmion Logic-In-Memory Architecture for Maximum/Minimum Search

In modern computing systems there is the need to utilize a large amount of data in maintaining high efficiency. Limited memory bandwidth, coupled with the performance gap between memory and logic, impacts heavily on algorithms performance, increasing the overall time and energy required for computation. A possible approach to overcome such limitations is Logic-In-Memory (LIM). In this paper, we propose a LIM architecture based on a non-volatile skyrmion-based recetrack memory. The architecture can be used as a memory or can perform advanced logic functions on the stored data, for example searching for the maximum/minimum number. The circuit has been designed and validated using physical simulations for the memory array together with digital design tools for the control logic. The results highlight the small area of the proposed architecture and its good energy efficiency compared with a reference CMOS implementation

Numerical Model for 32-Bit Magnonic Ripple Carry Adder

In CMOS-based electronics, the most straightforward way to implement a summation operation is to use the ripple carry adder (RCA). Magnonics, the field of science concerned with data processing by spin waves and their quanta magnons, recently proposed a magnonic half-adder that can be considered as the simplest magnonic integrated circuit. Here, we develop a computation model for the magnonic basic blocks to enable the design and simulation of magnonic gates and magnonic circuits of arbitrary complexity and demonstrate its functionality on the example of a 32-bit integrated RCA. It is shown that the RCA requires the utilization of additional regenerators based on magnonic directional couplers with embedded amplifiers to normalize the magnon signals in-between the half-adders. The benchmarking of large-scale magnonic integrated circuits is performed. The energy consumption of 30 nm-based magnonic 32-bit adder can be as low as 961 aJ per operation with taking into account all required amplifiers