52 research outputs found
Técnicas de inyección de fallos basadas en FPGAs para la evaluación de la tolerancia a fallos de tipo SEU en circuitos digitales
Este trabajo de tesis doctoral presenta nuevas técnicas de inyección de fallos
transitorios en elementos de memoria, que permiten la evaluación del comportamiento
de los complejos circuitos digitales actuales en presencia de fallos SEU (Single Event
Upset).
Se han propuesto técnicas de inyección que dan solución a la evaluación de la
tolerancia a fallos SEU para distintos componentes de los sistemas digitales actuales, en
los que se tiende a integrar distintos tipos de circuitos en un mismo chip, SoCs (System
on Chip). El entorno de inyección en las soluciones propuestas en esta tesis se basa en
emulación con dispositivos programables, FPGAs, realizándose las tareas relacionadas
con la inyección desde la plataforma hardware de emulación. La implementación
hardware del sistema de inyección minimiza la comunicación necesaria entre el
hardware y un computador, siendo dicha comunicación la mayor limitación en la
velocidad del proceso de inyección. En primer lugar, se presenta una técnica de
inyección de fallos basada en la emulación de fallos con FPGA, que permite evaluar un
circuito digital cuando se dispone de su descripción en un lenguaje de alto nivel, como
VHDL. Por otro lado, se propone una solución para la inyección de fallos en circuitos
microprocesadores basada en el uso de la infraestructura de depuración integrada en el
propio microprocesador (OCD, On-Chip Debugger), para acceder a sus recursos
internos (memorias y registros), en un componente comercial o prototipo final del
microprocesador.
Cuando se dispone de la descripción del circuito, éste se implementa junto con el
sistema de inyección en la FPGA y no es necesario establecer una comunicación con el
exterior durante el desarrollo de una campaña de inyección, por lo que esta propuesta se
ha denominado Emulación Autónoma. Al implementar el sistema completo de
inyección en un único dispositivo (la FPGA) se aumentan la observabilidad y
controlabilidad de los elementos del circuito. En este trabajo de investigación se han
propuesto optimizaciones del proceso de inyección, basadas en la mayor accesibilidad
al circuito que proporciona la Emulación Autónoma, para mejorar la eficiencia de las
tareas de inyección de fallos y observación del comportamiento del circuito en
presencia de fallos.
En esta tesis se describen y desarrollan tres implementaciones de técnicas de
inyección basadas en Emulación Autónoma, denominadas Time-Multiplexed, State-Scan
y Mask-Scan. Cada una de las tres implementaciones ofrece un compromiso distinto
entre velocidad del proceso de inyección y recursos necesarios para su aplicación. La
técnica Time-Multiplexed incluye el mayor número de optimizaciones y mejoras por lo
que es la técnica que mayor velocidad consigue en el proceso de evaluación pero, para
ello, requiere una cantidad de recursos también mayor que las otras dos
implementaciones. Las otras dos técnicas son simplificaciones de la primera, por lo que
utilizan menos recursos hardware en la emulación de fallos.
Además, se han desarrollado modelos de memoria que permiten aplicar la
técnica Time-Multiplexed a circuitos con memorias empotradas. Los modelos se basan
en controlar (para insertar los fallos) y observar (para detectar los errores y sus efectos)
el contenido de memoria a través de las señales de control, el bus de datos y el bus de
direcciones, evitando recorrer todas las palabras de datos. La inyección de fallos en
circuitos con memorias empotradas es un problema de gran interés, puesto que éstas
últimas son un componente cada vez más habitual en los diseños actuales. Además no
se había propuesto hasta la fecha ninguna solución eficiente para la emulación de fallos
en memorias. Esta aportación de la tesis permite inyectar fallos de forma rápida en
memorias empotradas resolviendo el problema de su limitada accesibilidad. También
para los modelos de memoria, se han propuesto distintas implementaciones en función
de las prestaciones conseguidas y recursos hardware necesarios, denominados modelo
Básico y modelo ECAM. El modelo Básico requiere menos recursos para su
implementación, mientras que el modelo ECAM proporciona una mayor capacidad de
análisis de los fallos.
Los experimentos realizados, tanto sobre circuitos de prueba como sobre
circuitos industriales reales, prueban que la Emulación Autónoma acelera el proceso de
inyección con respecto a otras soluciones propuestas, permitiendo inyectar millones de
fallos en unos pocos segundos. La aceleración conseguida es de dos órdenes de
magnitud, con la técnica Time-Multiplexed, con respecto a otras soluciones basadas en
emulación, que a su vez proporcionan una aceleración de cuatro órdenes de magnitud
con respecto a técnicas basadas en simulación. Esta notable aceleración en la inyección
de fallos permite evaluar circuitos de gran tamaño, como los circuitos actuales, donde
los posibles fallos suponen un número elevado, y para obtener una medida significativa
de su tolerancia a fallos es necesario inyectar un gran conjunto de fallos en un tiempo
razonable. Se ha comprobado experimentalmente la viabilidad de la solución presentada
para la inyección de fallos en memoria y las características de los modelos de memoria
propuestos, para ello se han realizado campañas de inyección sobre un microprocesador
industrial en el que se inyectan fallos tanto en los biestables como en la memoria.
Por otro lado, la técnica de inyección que se propone en la tesis orientada a
microprocesadores realiza la inyección de fallos y observación de sus efectos en el
circuito a través de su OCD. El avance de las capacidades e infraestructuras de
depuración en los microprocesadores actuales se debe al auge de SoCs y sistemas
empotrados en los que, de otra forma, el acceso para depuración a dicho componente
sería inviable o muy costoso. Estas capacidades proporcionan un mecanismo eficaz para
acceder a los recursos internos del microprocesador, necesario para realizar la inyección
de fallos y observar el comportamiento del circuito. El sistema de inyección propuesto
controla el OCD mediante su interfaz JTAG, el más común para acceder a los
microprocesadores actuales. Al igual que en el sistema de Emulación Autónoma, todas
las tareas de inyección se realizan desde el hardware, una FPGA, que se conecta al
microprocesador bajo estudio a través de su interfaz JTAG. Esta solución es aplicable a
cualquier microprocesador con OCD e interfaz JTAG, lo que son características
habituales en la actualidad.
Los experimentos desarrollados sobre microprocesadores comerciales (ARM y
PowerPC) demuestran que esta técnica proporciona una solución para la inyección de
fallos en componentes microprocesadores comerciales eficiente, de gran generalidad y
que alcanza un compromiso entre velocidad y coste.
En resumen, se ha propuesto una solución precisa, rápida y de bajo coste para
evaluar la tolerancia a fallos de tipo SEU de los circuitos digitales actuales, permitiendo
la inyección de fallos en circuitos de gran tamaño con memorias y microprocesadores
empotrados.
____________________________________________This PhD thesis presents new transient fault injection techniques to allow
evaluating the behaviour of complex digital circuits, as modern circuits, with transient
faults in memory elements, i.e., SEU (Single Event Upset) faults.
Fault injection techniques have been proposed to solve SEU tolerance evaluation
in different components of systems on chip (SoCs). The fault injection environment of
the proposed solutions in this thesis is emulation-based with FPGA, performing
injection tasks from the emulation hardware platform. The hardware implementation of
the injection system minimises the required communication between hardware and host
computer that is a bottleneck in speed injection process. First of all, a transient fault
emulation technique in FPGA devices aimed at evaluating a circuit, whose description
is available in a hardware description language (as VHDL), is presented. Secondly, a
fault injection technique aimed at evaluating fault tolerance in microprocessors is
proposed. Such proposal is applied on a final prototype or a commercial component and
it consists in using the debugger infrastructure integrated in the circuit (OCD, On-Chip
Debugger) to access the microprocessor’s internal resources (memory and registers).
On the one side, when the circuit description is available, the circuit is
implemented in the FPGA together with the injection system and therefore the
communication with the host PC is avoided during fault injection campaign. This fault
injection technique has been called Autonomous Emulation. The monolithic hardware
implementation for the injection system (a unique FPGA) provides better controllability
and observability of the circuit under test, than other solutions. Some injection process
optimisations are proposed in this research work in order to enhance the efficiency and
the speed of the different injection tasks.
In this work, three implementations of the Autonomous Emulation system are
proposed and developed. They are called Time-Multiplexed, State-Scan and Mask-
Scan. Each one provides a different trade-off between area overhead and injection
process speed-up. Time-Multiplexed technique includes more optimisations than the
other techniques. Therefore, it obtains the highest speed-up in the evaluation process,
but it requires more area overhead than the other implementations. State-Scan and
vi
Mask-Scan techniques are simplified versions of Time-Multiplexed implementation,
using less hardware resources to perform the fault emulation.
Furthermore, memory models have been developed in order to apply the Time-
Multiplexed technique to digital circuits with embedded memories. Such models are
based on controlling (to insert faults) and observing (to detect the errors and watch their
effects) the memory data by means of the control signals, data bus and memory address
bus, instead of accessing every memory word, that is a slow task, specially for large
memories. The fault injection in embedded memories is a very interesting problem as
they are components more and more usual in current digital designs. Besides, there is
not an efficient solution for fault emulation in memories in the literature. This thesis’
contribution allows the fault injection in embedded memories in a fast way, solving the
accessibility limitation problem. Different implementations have been also proposed for
the memory models, according to the trade-off between performance and hardware
resources requirements; they are named basic model and ECAM model. The basic
model involves less hardware resources, whilst the ECAM model provides a better
performance in the result analysis task.
The experiments developed in this thesis consist in performing fault injection
campaigns in benchmark circuits as well as in real ones. The experimental results prove
that Autonomous Emulation speeds-up the injection process with respect to other
existing solutions, making possible the injection of millions of faults in a few seconds.
The injection process speed increases around two orders of magnitude using Time-
Multiplexed with respect to other emulation-based solutions, what are faster than
simulation-based techniques in four orders of magnitude. This notable enhancement in
the injection speed allows the evaluation of the fault tolerance in large circuits, as the
current ones. In modern circuits, all the possible SEU faults suppose a very high number
of faults, and in order to obtain a significant measurement of the fault tolerance,
injecting a large set of faults in reasonable time is necessary. The feasibility of the
proposed memory models has also been analyzed performing fault campaigns in an
industrial microprocessor, injecting faults in flip-flops as well as in memory.
On the other side, the fault injection technique, proposed in this PhD thesis,
aimed at evaluating microprocessors using the OCD to insert the faults and to observe
their effects in the circuit. Nowadays, enhanced debugging capabilities and integrated
infrastructures are available in current microprocessors, due to the increasing use of
SoCs and embedded systems, where, without an OCD, the debugging process would be
infeasible or require a high cost. The OCD provides a mechanism to access
microprocessor’s internal resources and so it can be used to inject faults and to observe
the circuit behaviour. The proposed fault injection system controls the OCD by means
of the JTAG interface, what is the most common interface to access modern microprocessors. As in the Autonomous Emulation System, all the injection tasks are
performed in hardware, in an FPGA, that is connected to the microprocessor under test
by means of the JTAG interface. This solution could be applicable to any
microprocessor circuit with an OCD and a JTAG interface, what are the most common
features nowadays.
Developed experiments in commercial microprocessors (ARM and PowerPC)
show this technique provides an efficient solution to inject faults in microprocessors
devices, applicable to a wide range of different processors and offering a trade-off
between the injection process speed and its cost.
In summary, a fast, accurate and low cost solution to evaluate the SEU fault
tolerance in modern digital circuits has been proposed. It allows fault injection in large
circuits with embedded memories and microprocessors
Autonomous fault emulation: a new FPGA-based acceleration system for hardness evaluation
The appearance of nanometer technologies has produced a significant increase of integrated circuit sensitivity to radiation, making the occurrence of soft errors much more frequent, not only in applications working in harsh environments, like aerospace circuits, but also for applications working at the earth surface. Therefore, hardened circuits are currently demanded in many applications where fault tolerance was not a concern in the very near past. To this purpose, efficient hardness evaluation solutions are required to deal with the increasing size and complexity of modern VLSI circuits. In this paper, a very fast and cost effective solution for SEU sensitivity evaluation is presented. The proposed approach uses FPGA emulation in an autonomous manner to fully exploit the FPGA emulation speed. Three different techniques to implement it are proposed and analyzed. Experimental results show that the proposed Autonomous Emulation approach can reach execution rates higher than one million faults per second, providing a performance improvement of two orders of magnitude with respect to previous approaches. These rates give way to consider very large fault injection campaigns that were not possible in the past.This work was supported by the Directorate of Research of Madrid Community Government, Spain (Code 07/0052/2003 2) and by the European Commission and Spanish Government under MEDEA+ Project (PARACHUTE-2A701) and PROFIT Project (CIRCE-FIT-330100-2005-60)
Extensive SEU impact analysis of a PIC microprocessor for selective hardening
In order to increase the robustness of a circuit against SEUs, fault injection is commonly used to locate weak areas. autonomous emulation is a very powerful tool to locate these areas by executing huge fault injection campaigns. In this work, fault injection has been extensively applied to a PIC18 microprocessor, while executing three different workloads. A 80 million fault campaign has been performed, and results show that a failure rate lower than 1% can be obtained by hardening a 24% of the circuit flip-flops, for the given applications
HW/SW Co-Simulation System for Enhancing Hardware-in-the-Loop of Power Converter Digital Controllers
Digital controllers of power converters are more and more implemented in FPGAs due to the increasing complexity of current control algorithms, higher switching frequencies, and concurrence requirements. System behavior depends not only on the control algorithm but also on the implementation issues. Thus, closed-loop controller evaluation at early design stages is a main concern. In this paper, a new hardware-in-the-loop method is proposed. It profits from FPGAs and their design tools in order to validate the closed-loop power converter before prototyping the power stage. The proposed solution presents a general architecture that does not depend on specific vendors or CAD tools, but it uses those utilized for the final implementation of the controller. A case study is presented with a given implementation of the proposed solution. Comparisons with existing alternatives show the advantages of our approach
SEU Sensitivity Comparison for Different Reprogrammable Technologies With Minority Check Block
In this work, a method is proposed for obtaining comparable measurements of the SEU sensitivity in reprogrammable devices that present different characteristics like internal architecture, technology, amount of available resources, etc. A specific minority checker is developed for reporting the presence of SEUs or MBUs which will help in this comparing task during dynamic tests.This work was supported in part by the Spanish Ministry of Science and Technology, code TEC2010-22095-C03-03. RENASER+ projec
Hardware Fault Injection
Hardware fault injection is the widely accepted approach to evaluate the behavior
of a circuit in the presence of faults. Thus, it plays a key role in the design of robust
circuits. This chapter presents a comprehensive review of hardware fault injection
techniques, including physical and logical approaches. The implementation of
effective fault injection systems is also analyzed. Particular emphasis is made
on the recently developed emulation-based techniques, which can provide large
flexibility along with unprecedented levels of performance. These capabilities
provide a way to tackle reliability evaluation of complex circuits.Publicad
Horizontal and vertical contexts in Europeans’ well-being
Trabajo presentado al 14th International Workshop on Spatial Econometrics and Statistics celebrado en Paris (Francia) del 27 al 28 de mayo de 2015.Peer reviewe
Macro and micro determinants of well-being in European regions from a social capital perspective
Trabajo presentado al 55th European Regional Science Association Congress: "World Renaissance: Changing roles for people and places" celebrado en Lisboa (Portugal) del 25 al 28 de agosto de 2015.During the last years, happiness has received an increasing attention in the empirical literatures of Psychology, Sociology and Economics. In addition, a growing number of studies have focused on social capital. Most of this research analyzes survey data on life satisfaction and/or happiness at the individual level, some of them study the regional and national happiness, alternatively, both micro and macro determinants of individual happiness can be jointly studied through multilevel (or hierarchical) modelling.N
On the use of embedded debug features for permanent and transient fault resilience in microprocessors
Microprocessor-based systems are employed in an increasing number of applications where dependability is a major constraint. For this reason detecting faults arising during normal operation while introducing the least possible penalties is a main concern. Different forms of redundancy have been employed to ensure error-free behavior, while error detection mechanisms can be employed where some detection latency is tolerated. However, the high complexity and the low observability of microprocessors internal resources make the identification of adequate on-line error detection strategies a very challenging task, which can be tackled at circuit or system level. Concerning system-level strategies, a common limitation is in the mechanism used to monitor program execution and then detect errors as soon as possible, so as to reduce their impact on the application. In this work, an on-line error detection approach based on the reuse of available debugging infrastructures is proposed. The approach can be applied to different system architectures profiting from the debug trace port available in most of current microprocessors to observe possible misbehaviors. Two microprocessors have been used to study the applicability of the solution. LEON3 and ARM7TDMI. Results show that the presented fault detection technique enhances observability and thus error detection abilities in microprocessor-based systems without requiring modifications on the core architecture
Sensitivity Evaluation Method for Aerospace Digital Systems with Collaborative Hardening
Complexity of current digital systems and circuits involves new challenges in the field of hardening and measuring circuits sensitivity under SEEs. In this work, a new solution for evaluating the SEU sensitivity of space systems based on using programmable logic devices is proposed. This solution is able to perform a deep analysis of fault effects in systems with hardware functionality distribution, taking into account the high complexity of the hardware nodes (complex programmable logic devices) and their collaborative hardening properties
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