A transimpedance amplifier using a novel current mode feedback loop

We present a transimpedance amplifier stage based on a novel current mode feedback topology. This circuit employs NMOS and PMOS transistors exclusively and requires neither capacitor for stabilizing the transimpedance loop nor resistor for the transresistance feedback and transistor loading. This amplifier circuit is fully compatible with submicron digital CMOS processes. The active feedback network consists of two grounded-gate MOS devices which split the output current in both the feedback and output branches. The transresistance and the phase margin are adjustable through external DC signals. The measured rise time of the impulse response of the amplifier implemented in an industrial 0,7µm CMOS process is 18 ns for a transresistance of 180 k and 30 ns for a transresistance of 560 k. The measured Equivalent Noise Charge (ENC) is 800 rms e¯ for an input capacitance of 20 pF with the transresistance adjusted to 560 k

CARIOCA: a fast binary front-end implemented in 0.25μ0.25\mu CMOS using a Novel current-mode technique for the LHCb muon detector

The CARIOCA front-end is an amplifier discriminator chip, using 0.25mm CMOS technology, developed with a very fast and low noise preamplifier. This prototype was designed to have input impedance below 10W. Measurements showed a peaking time of 14ns and noise of 450e- at zero input capacitance, with a noise slope of 37.4 e-/pF. The sensitivity of 8mV/fC remains almost unchanged up to a detector capacitance of 120pF

SCTA - A Rad-Hard BiCMOS Analogue Readout ASIC for the ATLAS Semiconductor Tracker

Two prototype chips for the analogue readout of silicon strip detectors in the ATLAS Semiconductor Tracker (SCT) have been designed and manufactured, in 32 channels and 128 channel versions, using the radiation hard BiCMOS DMILL process. The SCTA chip comprises three basic blocks: front-end amplifier, analogue pipeline and output multiplexer. The front-end circuit is a fast transresistance amplifier followed by an integrator, providing fast shaping with a peaking time of 25 ns, and an output buffer. The front end output values are sampled at 40 MHz rate and stored in a 112-cell deep analogue pipeline. The delay between the write pointer and trigger pointer is tunable between 2 ms and 2.5 ms. The chip has been tested successfully and subsequently irradiated up to 10 Mrad. Full functionality of all blocks of the chip has been achieved at a clock frequency of 40 MHz both before and after irradiation. Noise figures of ENC = 720 e- + 33 e-/pF before irradiation and 840 e- + 33 e-/pF after irradiation have been obtained

A low power, large dynamic range, CMOS amplifier and analog memory for capacitive sensors

This paper has been written to announce the design of a CMOS charge to voltage amplifier and it¹s integration within an analog memory. Together they provide the necessary front end electronics for the CMS electromagnetic calorimeter (ECAL) preshower detector systeAspell,Pm in the LHC experiment foreseen at the CERN particle physics laboratory. The design and measurements of the amplifier realised in a 1.5mm bulk CMOS process as a 16 channel prototype chip are presented. Results show the mean gain and peaking time of = 1.74mV/mip, = 18ns with channel to channel variations; s(peak_voltage) = 8% and s(peak_time) = 6.5%. The dynamic range is shown to be linear over 400mips with an integral non linearity (INL)=0.05mV as expressed in terms of sigma from the mean gain over the 400mip range. The measured noise of the amplifier was ENC=1800+41e/pF with a power consumption of 2.4mW/channel. The amplifier can support extreme levels of leakage current. The gain remains constant for up to 200mA of leakage current. The integration of this amplifier within a 32 channel, 128 cell analog memory chip ³DYNLDR² is then demonstrated. The DYNLDR offers sampling at 40MHz with a storage time of up to 3.2ms. It provides continuous Write/Read access with no dead time. Triggered data is protected within the memory until requested for readout which is performed at 2.5MHz. The memory is designed to have a steerable dc level enabling maximum dynamic range performance. Measurements of the DYNLDR are presented confirming the original amplifier performance. The memory itself has a very low pedestal non uniformity (s(ped)) of 0.9mV and a gain of 10mV/mip

Micro-Channel Plate Detectors Based on Hydrogenated Amorphous Silicon

A new type of micro-channel plate detector based on hydrogenated amorphous silicon is proposed which overcomes the fabrication and performance issues of glass or bulk silicon ones. This new type of detectors consists in 80-100 μm thick layers of amorphous silicon which are micro-machined by deep reactive ion etching to form the channels. This paper focuses on the structure and fabrication process and presents first results obtained with test devices on electron detection which demonstrate amplification effects. Fabrication and performance issues are also discussed