Bonivento, W

Dos Santos, F

Jarron, Pierre

Moraes, D

Riegler, W

CERN Document Server

Status of the CARIOCA ProjectW. Bonivento1,2, D. Moraes1,3, P. Jarron1, W. Riegler1, F. dos Santos11 CERN, 1211 Geneva 23, Switzerland2 Instituto Nazionale di Fisica Nucleare,Sezione di Cagliari, Italy                                           3 LAPE – IF/UFRJ, CP 68528 Cidade Univ., Ilha do Fundão BR-21945970 Rio de Janeiro, Brazil.Walter.Bonivento@cern.ch, Danielle.Moraes@cern.chAbstractCARIOCA is an amplifier shaper discriminator chip,developed in IBM 0.25µm CMOS for the readout of theLHCb muon wire chambers. Four prototype chips weredesigned and fabricated over the last two years with a stepby step approach testing the different functionalities ofthe chip. In this paper the design and test results of apositive polarity and negative polarity amplifier, as wellas a shaper circuit, are discussed.I. INTRODUCTIONThe LHCb muon system will use 80,000 wirechamber channels of negative (wire readout) and positive(cathode readout) polarity. Figure 1 shows the blockdiagram for one readout channel.Figure 1: Block diagram of one readout channelThe chamber signal, with a fast rising edge and a long1/t tail, is amplified and shaped to a unipolar narrow pulsein order to cope with the high rate expected in theexperiment. A baseline restoration circuit is needed tocompensate for baseline shifts and fluctuations. Thecircuit is fully differential from the shaper on.To this date the positive and negative amplifiers aswell as shaper and discriminator have been designed andfabricated. The results of a 4-channel version of thepositive polarity amplifier are presented in [1], togetherwith the chip specifications. In this report we presentmeasurements of a 14-channel positive amplifier chip andresults of the negative polarity amplifier and the shaper.II. THE 14-CHANNEL POSITIVE POLARITYAMPLIFIERThe main purpose of the 14-channel chip was to test chipuniformity and crosstalk. The individual channels showlinearity up to an injected charge of 200fC (delta input),with a non-linearity error of about 1%. The measuredsensitivity is 8mV/fC up to a detector capacitance of140pF and we find an equivalent noise charge ofENC=867e- + 36e-/pF. The sensitivities of all 14-channelswere found to be within 10%. The noise and thresholdvariation was measured to be 7% R.M.S. The crosstalk issmaller than 1%. The power consumption of about 18mWper channel is dominated by LVDS driver.III. THE NEGATIVE POLARITY AMPLIFIERA. DesignThe design of the negative polarity amplifier followsclosely that of the positive one [1]. Figure 2 shows asimplified schematic. The input stage is a cascodestructure (N1) with a large input transistor that isfollowed by a voltage to current converter (N0) and acurrent mirror (N2). The mirror feeds the current to theoutput stage (N4) and back to the input stage. The outputcurrent is finally converted into voltage that is driven tothe chip pad by an analog buffer. The size of thetransistors N3 and N4 determines the current gain ofabout 6.Figure 2: Simplified schematic of the negativepolarity amplifier.From CADENCE simulation the bandwidth wasfound to be 16MHz and 23MHz for the negative andpositive amplifier, respectively. The input impedance isbelow 50Ω within the bandwidth.B. MeasurementsThe circuit displays linearity within 1% up to 200fC.Results of peaking time, sensitivity and noisemeasurements vs. detector capacitance, together withCADENCE simulation, are shown in Figure 3, 4 and 5,.The fit to the points of figure 5 gives a noise ofENC=951e-+31e-/pF.Figure 3: Measured (black dots) and simulated (whitedots) peaking time vs. detector capacitance for thenegative polarity amplifier.Figure 4: Measured (black dots) and simulated (whitedots) sensitivity vs. detector capacitance for the negativepolarity amplifier.Figure 5: Measured equivalent noise charge vs. detectorcapacitance for the negative polarity amplifier.IV. THE SHAPERC. DesignThe shaper is a differential amplifier in a folded cascodeconfiguration with common mode feedback. A simplifiedschematic is shown in Figure 6. The shaper is designedwith a speed such that the amplifier peaking time is notsignificantly degraded. Therefore the dominant highfrequency pole is located at 160MHz. The 1/t tailcancellation is performed by a double pole/zerocompensation network [2][3] displayed in Figure 7.Figure 6: Simplified schematic of the shaper circuit.Figure 7: Schematic of the pole/zero compensationnetwork.D. MeasurementsThe prototype chip uses two positive polarity amplifiersfollowed by the shaper. The differential shaper outputwas equipped with two analog buffers and only one ofthem was read out during the tests.Figure 8 and 9 show the measured peaking timeand noise versus detector capacitance for two differentbias currents configurations. For high bias current a noiseperformance of ENC=1290e-+40e- is achieved.The offset ENC is higher than that of thepositive amplifier alone due to the presence of twoamplifiers at the shaper input. The slope is consistent withthat of the positive amplifier chip but higher than that ofthe negative amplifier due to the large bandwidth of theshaper.Figure 8: Measured (black symbols) and simulated (whitesymbols) peaking time of the shaper chip as a function ofdetector capacitance for a delta input. The triangles anddots correspond to two different bias currentconfigurations.Figure 9: Measured equivalent noise charge of the shaperchip as a function of detector capacitance. The trianglesand dots correspond to two different bias currentconfigurations.A quasi-1/t current injector, realised with fourparallel RC circuits, was used to simulate a detectorpulse. Figure 10 shows the output pulse from the negativeamplifier and displays a long tail. Figure 11 shows theoutput pulse from the shaper with the same time scale ofFigure 10 indicating that the tail is to large extentsuppressed.Figure 12 shows the peaking time versus detectorcapacitance with the 1/t injector.The pulse width (at 20% amplitude) was foundto be less than 30ns after shaping up to 200pF detectorcapacitance.Figure 10: Output of the negative polarity amplifier for a1/t current pulse input.Figure 11: Shaper output for a 1/t current pulse input.Figure 12: Measured (black dots) and simulated (whitedots) peaking time of the shaper chip as a function ofdetector capacitance for a 1/t current pulse input.V. CONCLUSIONS AND FUTURE PLANSFour prototype chips of the CARIOCA front-end havebeen produced during the last two years. Positive andnegative amplifier and shaper circuits were tested andtheir characteristics satisfy the requirements for operationin LHCb. A final prototype, including a baselinerestoration circuit, will be submitted in November 2001.The overall goal is to start chip production by the end of2002.VI. ACKNOWLEDGEMENTThis work has been partially supported by ConselhoNacional de Desenvolvimento Científico e Tecnológico(CNPq-Brazil) and by the European Commission(contract CT1* - CT94 - 0118).VII. REFERENCES[1] D.Moraes, “CARIOCA – a fast binary front-endimplemented in 0.25um CMOS using a novel current-mode technique for the LHCb Muon detector”,presented at LEB2000.[2] R.A.Boie et al., “Signal shaping and tail cancellationfor gas proportional detectors at high counting rates”,Nucl. Instr. and Meth. 192 (1982) 365.[3] M. Newcomer, “Progress in development of theASDBLR ASIC for the ATLAS TRT”, presented atLEB1999.

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