The CARIOCA front-end is an amplifier discriminator chip, using 0.25mm CMOS technology, developed with a very fast and low noise preamplifier. This prototype was designed to have input impedance below 10W. Measurements showed a peaking time of 14ns and noise of 450e- at zero input capacitance, with a noise slope of 37.4 e-/pF. The sensitivity of 8mV/fC remains almost unchanged up to a detector capacitance of 120pF

Anghinolfi, Francis

Deval, P

Jarron, Pierre

Moraes, D

Riegler, W

Rivetti, A

Schmidt, B

Anghinolfi, F

Jarron, P

CERN Document Server

CARIOCA - a fast binary front-end implemented in 0.25 $\mu$m CMOS using a Novel current-mode technique for the LHCb muon detector

CARIOCA - A Fast Binary Front-End Implemented in 0.25m CMOS using a NovelCurrent-Mode Technique for the LHCb Muon DetectorD. Moraes1, F. Anghinolfi2, P. Deval3, P. Jarron2, W. Riegler2, A. Rivetti2, B. Schmidt21 LAPE – IF/UFRJ, CP 68528 Cidade Univ., Ilha do Fundão BR-21945970 Rio de Janeiro, Brazil.2 CERN, 1211 Geneva 23, Switzerland.3 MEAD Microlectronics S.A., Venoge 7, 1025 St. Sulpice, Switzerland.danielle@if.ufrj.brAbstractThe CARIOCA front-end is an amplifier discriminatorchip, using 0.25Pm CMOS technology, developed with avery fast and low noise preamplifier. This prototype wasdesigned to have input impedance below 10:.Measurements showed a peaking time of 14ns and noiseof 450e- at zero input capacitance, with a noise slope of37.4 e-/pF. The sensitivity of 8mV/fC remains almostunchanged up to a detector capacitance of 120pF.I. INTRODUCTIONThe investigation of the characteristics of state-of-the-art deep submicron CMOS technologies show thatanalogue circuits with very good performance can bedesigned using these processes. In particular, deepsubmicron technologies are well suited for the design ofbinary front-end systems. In these applications, thelimitation on the dynamic range imposed by the squeezedpower supplies is not the primary issue [1-3].Current-mode architectures are an attractivealternative to the more conventional voltage-mode onesfor very fast circuits. In the current mode approach, thesignal is processed in the current domain, thus avoidingcharging and discharging of the parasitic capacitance to“high” voltage levels and keeping the internal nodes ofthe circuit at low impedance values. Therefore,combining current-mode techniques with the use of deepsubmicron technologies provides the opportunity ofbuilding analog circuits with high speed and low powerconsumption.The front-end CARIOCA has been designed in twoversions: one optimised for the readout of the Multi WireProportional Chambers (MWPC) of the LHCb Muonsystem [4] and the other for silicon strip detectors. Thispaper presents only the requirements and results for theLHCb muon chambers, which is the more challenging interms of detector capacitance up to 200pF. This work hasbeen done in the framework of the CERN RD49 project[5].II. FRONT - END REQUIREMENTSThe LHCb Muon System [6] is composed of fivemuon detector stations, which provide muonidentification and Level-0 muon trigger formation. Eachstation is required to have an efficiency above 99% withina 20ns time window. This translates into a time resolutionof 3.5ns (rms) for the double gap MWPCs with a wirespacing of 1.5mm.The total number of MWPC is approximately 600,which corresponds to 125K readout channels. High ratesof up to 800KHz per channel in some detector regionsrequire optimised tail cancellation and baselinerestoration circuits. The maximum integrated dose in theMuon system is of 1Mrad requiring radiation hardtechnology.The capacitances of the MWPCs range from about10pF to 200pF. This capacitance together with thepreamplifier input resistance define a time constant,ininin CR  , that ultimately limits the front-end speed.In addition, an amplifier input resistance below 50: isrequired in order to limit the capacitive crosstalk.A good time resolution at a gas gain of about 2105requires a very low threshold combined with high speedand low noise front-end for detector capacitances up to200pF. Calculations [7] show that a peaking time of about10ns is a good compromise in terms of time resolutionand stability of the signal discrimination.III. CIRCUIT DESCRIPTIONFast low noise pulse amplifiers are usually based oncharge or transimpedance circuits, and have limitedperformance at large detector capacitance. This limitationis due to the fact that the feedback network, whichconverts the output voltage into an input current, musthave low impedance in order to keep the closed loop gainsmall enough to get a high speed response. As aconsequence, the charge-to-voltage gain is smaller andthe noise performance reduced. The present front-enduses a novel low noise current mode feedback circuit thatcan amplify current signals of large detector capacitancesat very high speed without having significantly morenoise than a charge amplifier.The prototype, shown in Figure 1, is a eight-channellow noise amplifier discriminator binary front-enddeveloped in a 0.25Pm CMOS technology, operating at2.5V. The present version of the CARIOCA front-end hasbeen optimised for detector capacitances up to 120pF.Each processing channel is formed by a current modepreamplifier, a three-stage discriminator and a LVDSdriver. The overall chain is DC, allowing very highcounting rate readout operation without baseline shifteffects. Only one signal return path is used (ground) to bemore robust on power supply rejection. Each channel hasan independent biasing and threshold circuit, which mayavoid crosstalk between channels. The analog structure ofa single channel is shown in Figure 2. The detailed circuitschematic is described in [8].Figure 1: Photo of the 2x2mm2 prototype with eight channels.Figure 2: CARIOCA block diagram.A. PreamplifierThe preamplifier, shown in Figure 3, is a n-channelstructure with an active feedback and a large inputtransistor with W/L of 1600Pm/0.7Pm. The drain currentof 2mA is determined by a p-channel cascode currentsource, with independent networks for the bias voltages.A current mirror follows the first stage of amplification.The transconductance ratio of the transistors 3N  and4N  gives the preamplifier current gain34NNmmINOUTggII  .Figure 3: Simplified preamplifier schematic.Due to the feedback, the input impedance is determinedby  121321 NNmmmIN RRgggR NNN  ,where 1NR  and 2NR  are the resistances on the drainnodes of the transistors 1N  and 2N . For mediumfrequencies the input resistance stays at about 10:.B. DiscriminatorThe discriminator consists of 3 stages: a currentdiscriminator, a voltage sensing amplifier and a bufferfollowed by a LVDS driver, as shown in Figure 4. Abaseline restoration based on a DC servo loop (notshown) ensures both dynamic stability of the baseline andoffset cancellation necessary with the fully DC coupledcircuit.Figure 4: Discriminator block diagram.IV. MEASUREMENT RESULTSMeasurements have been done for the CARIOCA lowgain version, optimised for an input capacitance of 120pF.Examples of analog and digital signals are shown inFigure 5 and 6, at an input capacitance of 15pF. Thepositive overshoot is due to the baseline restorationcircuit that produces a bipolar shape.It is important to notice that all measurements wereperformed using delta input with a rise time of 5ns thatmay reduce the preamplifier speed and sensitivity.Figure 5: CARIOCA analog output signals for input pulses from10fC to 40fC, at an input capacitance of about 15pF.Figure 6: CARIOCA digital output signals for input pulses from60fC to 100fC, at an input capacitance of about 15pF.A. Peaking timeFigure 7 shows the peaking time versus the detectorcapacitance. The measurement shows a peaking time of14ns at Cdet=0pF and a weak dependence with the inputcapacitance. The discrepancy with relation to thesimulation is of about 15%. If a delta input of 1ns risetime is considered, a 2ns reduction on the peaking timecan be obtained.The expected peaking time for the preamplifier aloneis about 8ns. The deterioration of the preamplifier speedis due to the increase of capacitance in the coupling withthe discriminator stage.CARIOCA ICDetector Capacitance [pF]Peaking time [ns]Figure 7: Preamplifier peaking time versus the inputcapacitance for measurement (closed circle) and simulation(open circle).B. SensitivityThe sensitivity, shown in Figure 8, was measured fordifferent detector capacitances and showed gooduniformity up to 120pF within 5% error. The preamplifiergain is about 8mV/fC using a delta input, as mentionedbefore. Good agreement between the simulation and themeasurement was found.CARIOCA ICDetector Capacitance [pF]Sensitivity [mV/fC]Figure 8: Preamplifier sensitivity as a function of the inputcapacitance. The measurements are shown as closed circle andsimulation as open circle.C. Noise versus Detector CapacitanceThe noise measurements were performed with adrain current of 2mA at the input transistor and a peakingtime of 14ns. The results are show in Figure 9 togetherwith the calculations. A parallel noise of 450e- wasmeasured. The noise slope is about 37.4e-/pF for inputcapacitance up to 50pF and 54.4e-/pF for highercapacitances. The noise slope difference for low and highcapacitance values is not fully understood. A briefcalculation has shown a parallel noise of 416e- with anoise slope of 35.9e-/pF and an equivalent input noisevoltage of 0.7nV/Hz. The flicker noise was estimated tobe 1.2e-/pF. The noise calculation was performedconsidering a weighting function with a bipolar shape, asdescribed in [9], and resulted in the following equationsfor the parallel, serial and flicker noise, respectively:22/122244inffinpeakmspeakppCAENCCtgKTnENCtRKTENCK is the Boltzman constant, T the absolute temperature,tpeak the signal peaking time and Cin the input capacitance.The parallel input resistance Rp is about 50K: and thegate transconductance of the input transistor gm is 30mS.The noise characteristics of 0.25Pm CMOS technology[10], n, J and Af , were estimated to be 1.4, 0.6 and 4.10-14V2/Hz, respectively.For RC-CR filters of 25ns, normally used inseveral LHC front-end circuits, the noise slope isapproximately 27e-/pF for low input capacitances and40.7e-/pF for high capacitances.CARIOCA ICDetector Capacitance [pF]Equivalent Noise Charge [e]Figure 9: Equivalent Noise Charge measured (closed circle) andcalculated (open circle) as a function of the detector capacitancefor a peaking time of 14ns. The slope obtained for lowcapacitance is 37.4e-/pF and for high capacitance 54.4e-/pF.Calculations showed a noise slope of 35.9e-/pF.The total power consumption was measured to be12mW per channel, including the discriminator andLVDS driver.The irradiation tests are not done yet, but previousresults using 0.25Pm CMOS technologies combined withenclosed layout transistors and guard-rings have shown avery good resistance to total dose radiation damage up to30MRad [11].V. CONCLUSIONS AND FUTURE PLANSAn eight-channel amplifier has been produced using0.25Pm CMOS technology. The tests of the four low gainchannels, optimised for 120pF of input capacitance, haveshown excellent agreement with the expected results fromsimulations.Noise measurements indicate an excellentperformance of the current mode feedback and agree withnoise calculations based on the models for 0.25PmCMOS technology.A new prototype with 14-channels of each low andhigh gain version will be produced to study channeluniformity and crosstalk. A 16-channel amplifier withshaper and baseline restoration circuits is underdevelopment. The final goal is a circuit for both anodeand cathode readout, optimised for an input capacitanceof up to 200pF with a faster discriminator.VI. ACKNOWLEDGEMENTThis work has been partially supported by ConselhoNacional de Desenvolvimento Científico e Tecnológico(CNPq-Brazil) and by the European Commission(contract CT1* - CT94 - 0118).VII. REFERENCES[1] P. Jarron, et al., “Deep Submicron CMOSTechnologies for the LHC experiments”, Nucl. Phys.B78, 1999, p.625.[2] A. Rivetti et al., “Analog Design in Deep SubmicronCMOS Processes for LHC”, Proceedings of the FifthWorkshop on Electronics for LHC Experiments,CERN/LHCC 99-33, 1999.[3] W. Snoeys et al. “Integrated Circuits for ParticlePhysics Experiments in the 21st Century”, Proceedingsof the IEEE International Solid State circuitsconference, 2000.[4] A. Vorobyov et al., “Wire Pad Chambers for theLHCb Muon System”, LHCb Internal Note 2000-003,2000.[5] P. Jarron et al., RD49 Project, “Study of the RadiationTolerance of ICs for the LHC”, CERN/LHCC 2000-003, 2000.[6] LHCb Technical Proposal, CERN/LHCC 98-4, 1998.[7] W. Riegler, “Detector Physics and PerformanceSimulations of the MWPCs for the LHCb MuonSystem”, LHCb Internal Note 2000-060.[8] D. Moraes, F. Anghinolfi, P. Deval, P. Jarron, W.Riegler, A. Rivetti, B. Schmidt, “A Fast Binary Front-End for sensor interface Implemented in 0.25PmCMOS using a Novel Current-Mode FeedbackTechnique”, to be presented in the 2001 IEEEInternational Symposium on Circuits and Systems.[9] V. Radeka, “Low Noise Techniques in Detectors”,Ann. Rev. Nucl. Part. Sci. 1988, 217-277.[10] G. Anelli, F. Faccio, S. Florian, P. Jarron, “Noisecharacterisation of a 0.25Pm CMOS technology forthe LHC experiments”, to be published in NuclearInstruments and Methods in Physics Research A.[11] G. Anelli et al., “Radiation Tolerant VLSI Circuits inStandard Deep Submicron CMOS technologies for theLHC Experiment: Practical Design Aspects”, IEEETrans. Nucl. Science 46, No.6, 1999.