Exploring Digital Evidence with Graph Theory

The analysis phase of the digital forensic process is the most complex. The analysis phase remains very subjective to the views of the forensic practitioner. There are many tools dedicated to assisting the investigator during the analysis process. However, they do not address the challenges. Digital forensics is in need of a consistent approach to procure the most judicious conclusions from the digital evidence. The objective of this paper is to discuss the ability of graph theory, a study of related mathematical structures, to aid in the analysis phase of the digital forensic process. We develop a graph-based representation of digital evidence and evaluate the relations between pieces of evidence. We determine possible techniques investigators will be able to use to examine digital evidence, as well as, explore how graph theory can be used as a basis for further analysis. Lastly, we demonstrate the potential of the application of graph theory through its implementation in a case study

Why don’t we eat more seafood?

A variety of factors combine to limit seafood consumption. Seafood is perceived to be expensive, and safety perceptions influence consumer buying decisions. Culture and tradition also play roles in forging seafood-eating habits. Smaller portions can reduce seafood prices, and information on the sources of seafood and safety assurances can help reduce risk perceptions. Industry best practices combined with consistent promotion of the health benefits of seafood can help improve consumer confidence and lead to increased seafood sales

Radial orbit instability as a dissipation-induced phenomenon

This paper is devoted to Radial Orbit Instability in the context of self-gravitating dynamical systems. We present this instability in the new frame of Dissipation-Induced Instability theory. This allows us to obtain a rather simple proof based on energetics arguments and to clarify the associated physical mechanism.Comment: 15 pages. Published in Monthly Notices of the RAS by the Royal Astronomical Society and Blackwell Publishing. Corrected for page style, typos, and added reference

Understanding Timing Error Characteristics From Overclocked Systolic Multiply–Accumulate Arrays in FPGAs

Artificial Intelligence (AI) hardware accelerators have seen tremendous developments in recent years due to the rapid growth of AI in multiple fields. Many such accelerators comprise a Systolic Multiply–Accumulate Array (SMA) as its computational brain. In this paper, we investigate the faulty output characterization of an SMA in a real silicon FPGA board. Experiments were run on a single Zybo Z7-20 board to control for process variation at nominal voltage and in small batches to control for temperature. The FPGA is rated up to 800 MHz in the data sheet due to the max frequency of the PLL, but the design is written using Verilog for the FPGA and C++ for the processor and synthesized with a chosen constraint of a 125 MHz clock. We then operate the system at a frequency range of 125 MHz to 450 MHz for the FPGA and the nominal 667 MHz for the processor core to produce timing errors in the FPGA without affecting the processor. Our extensive experimental platform with a hardware–software ecosystem provides a methodological pathway that reveals fascinating characteristics of SMA behavior under an overclocked environment. While one may intuitively expect that timing errors resulting from overclocked hardware may produce a wide variation in output values, our post-silicon evaluation reveals a lack of variation in erroneous output values. We found an intriguing pattern where error output values are stable for a given input across a range of operating frequencies far exceeding the rated frequency of the FPGA

Effective mobilities in pseudomorphic Si/SiGe/Si p-channel metal-oxide-semiconductor field-effect transistors with thin silicon capping layers

The room-temperature effective mobilities of pseudomorphic Si/Si0.64Ge0.36/Si p-metal-oxidesemiconductor field effect transistors are reported. The peak mobility in the buried SiGe channel increases with silicon cap thickness. It is argued that SiO2/Si interface roughness is a major source of scattering in these devices, which is attenuated for thicker silicon caps. It is also suggested that segregated Ge in the silicon cap interferes with the oxidation process, leading to increased SiO2/Si interface roughness in the case of thin silicon caps

Pervasive selection for and against antibiotic resistance in inhomogeneous multistress environments

Antibiotic-sensitive and -resistant bacteria coexist in natural environments with low, if detectable, antibiotic concentrations. Except possibly around localized antibiotic sources, where resistance can provide a strong advantage, bacterial fitness is dominated by stresses unaffected by resistance to the antibiotic. How do such mixed and heterogeneous conditions influence the selective advantage or disadvantage of antibiotic resistance? Here we find that sub-inhibitory levels of tetracyclines potentiate selection for or against tetracycline resistance around localized sources of almost any toxin or stress. Furthermore, certain stresses generate alternating rings of selection for and against resistance around a localized source of the antibiotic. In these conditions, localized antibiotic sources, even at high strengths, can actually produce a net selection against resistance to the antibiotic. Our results show that interactions between the effects of an antibiotic and other stresses in inhomogeneous environments can generate pervasive, complex patterns of selection both for and against antibiotic resistance