A Systolic Hardware Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems

The arithmetic in a finite field constitutes the core of Public Key Cryptography like RSA, ECC or pairing-based cryptography. This paper discusses an efficient hardware implementation of the Coarsely Integrated Operand Scanning method (CIOS) of Montgomery modular multiplication combined with an effective systolic architecture designed with a Two-dimensional array of Processing Elements. The systolic architecture increases the speed of calculation by combining the concepts of pipelining and the parallel processing into a single concept. We propose the CIOS method for the Montgomery multiplication using a systolic architecture. As far as we know this is the first implementation of such design. The proposed architectures are designed for Field Programmable Gate Array platforms. They targeted to reduce the number of clock cycles of the modular multiplication. The presented implementation results of the CIOS algorithms focuses on different security levels useful in cryptography. This architecture have been designed in order to use the flexible DSP48 on Xilinx FPGAs. Our architecture is scalable and depends only on the number and size of words. For instance, we provide results of implementation for 8, 16, 32 and 64 bit long words in 33, 66, 132 and 264 clock cycles. We highlight the fact that for a given number of word, the number of clock cycles is constant

Fetal outcome in emergency versus elective cesarean sections at Souissi Maternity Hospital, Rabat, Morocco

Introduction: Perinatal mortality rates have come down in cesarean sections, but fetal morbidity is still high in comparison to vaginal delivery and the complications are more commonly seen in emergency than in elective cesarean sections. The objective of the study was to compare the fetal outcome and the indications in elective versus emergency cesarean section performed in a tertiary maternity hospital. Methods: This comparative cross-sectional prospective study of all the cases undergoing elective and emergency cesarean section for any indication at Souissi maternity hospital of Rabat, Morocco, was carried from January 1, to February 28, 2014. Data were analyzed with emphasis on fetal outcome and cesarean sections indications. Mothers who had definite antenatal complications that would adversely affect fetal outcome were excluded from the study. Results: There was 588 (17.83%) cesarean sections among 3297 births of which emergency cesarean section accounted for 446 (75.85%) and elective cesarean section for 142 cases (24.15%). Of the various factors analyzed in relation to the two types of cesarean sections, statistically significant associations were found between emergency cesarean section and younger mothers (P < 0.001), maternal illiteracy (P = 0.049), primiparity (P = 0.005), insufficient prenatal care (P < 0.001), referral from other institution for pregnancy complications or delivery (P < 0.001), cesarean section performed under general anesthesia (P < 0.001), lower birth weight (P < 0.016), neonatal morbidity and early mortality (P < 0.001), and admission in neonatal intensive care unit (P = 0.024). The commonest indication of emergency cesarean section was fetal distress (30.49%), while the most frequent indication in elective cesarean section was previous cesarean delivery (47.18%). Conclusion: The overall fetal complications rate was higher in emergency cesarean section than in elective cesarean section. Early recognition and referral of mothers who are likely to undergo cesarean section may reduce the incidence of emergency cesarean sections and thus decrease fetal complications.Pan African Medical Journal 2016; 2

Implémentation efficace de primitive cryptographique pour le couplage sur carte FPGA

Le défi primaire dans le développement matériel de la cryptographie moderne est de faire des implémentations optimales en ressources, et rapide, en garantissant une résistance contre les attaques. Cette recherche porte sur les implémentations pratiques des opérations de cryptographie basées sur la cryptographie à clé publique dans les corps finis. Durant cette thèse nous avons proposé des composants matériels de base. L'arithmétique des corps finis constitue le noyau de la cryptographie à clé publique comme RSA, ECC ou une cryptographie basée sur le couplage. Nous avons proposé dans cette thèse des architectures du calcul arithmétique haute performance pour implémenter les primitives de cryptographie asymétrique. Les composants décrits dans notre travail ont été implémentés dans des Field Programmable Gate Array platforms (FPGA) de Xilinx. Nous avons utilisé le VHDL pour développer nos composants et nos architectures. Nos résultats présentent des performances en ressources et en vitesse jamais égalées auparavant dans la littérature publique sur ce type de technologie. La particularité de ces architectures est l'utilisation de l'architecture systolique pour développer une multiplication modulaire. Cette thèse traite la mise en œuvre matérielle efficace de la méthode CIOS (Coarsely Integrated Operand Scanning) de la multiplication modulaire de Montgomery combinée avec une architecture systolique efficace. D'après nos connaissances, c'est la première implémentation d'une telle conception. Nos architectures visaient à réduire le nombre de cycles d'horloge de la multiplication modulaire. Les résultats d'implémentation des algorithmes CIOS se concentrent sur différents niveaux de sécurité utiles en cryptographie. Cette architecture a été conçue pour utiliser le DSP48 flexible sur les FPGA de Xilinx. Nos architectures sont évolutives et dépendent uniquement du nombre et de la taille des mots. Par exemple, nous fournissons des résultats d'implémentation pour des longs mots de 8, 16, 32 et 64 bits en 33, 66, 132 et 264 cycles d'horloge. Nous décrivons également un design pour calculer une inversion et/ou une division dans Fp. L'inversion peut être utilisée dans les systèmes de la cryptographie de courbe elliptique et de la cryptographie basée sur le couplage.The primary challenge in the hardware development of the modern cryptography is to make an optimal implementations in resources and speed, with guaranteeing a resistance against attacks. This research focuses on practical implementations of cryptographic operations based on public key cryptography in finite fields. During this thesis we proposed basic hardware components. Finite field arithmetic is the core of public key cryptography such as RSA, ECC, or pairing-based cryptography. We proposed in this thesis a high-performance architectures of arithmetic calculation to implement asymmetric cryptographic primitives. The components described in this thesis have been implemented in Xlinx Field Programmable Gate Array Platforms (FPGAs). We used the VHDL to devolve our components and architectures. Our results show a performance and speed never presented before in the literature on this type of technology. The particularity of these architectures is the use of systolic architecture to develop a modular multiplication. This thesis deals with the effective physical implementation of the Coarsely Integrated Operand Scanning (CIOS) method of Montgomery's modular multiplication combined with an effective systolic architecture. According to our knowledge, this is the first implementation of such a design. Our architectures were aimed at reducing the number of clock cycles of modular multiplication. The implementation results of the CIOS algorithms focus on different levels of security useful in cryptography. This architecture was designed to use the flexible DSP48 on Xilinx FPGAs. Our architectures are scalable and depend only on the number and size of the words. For instance, we provide implementation results for 8, 16, 32, and 64 bit long words in 33, 66, 132, and 264 clock cycles. We describe also a design to compute an inversion in Fp as well as division. Inversion can be used in Elliptic Curve Cryptography systems and pairing-based cryptography

Algorithmic accelerations for wave impacts numerical simulation. Roofline type models for the performance characterization, application to CFD

Au cours de ces dernières années les processeurs sont devenus de plus en plus complexes (plusieurs niveaux de cache, vectorisation,...), l’augmentation de la complexité fait que l’étude des performances et les optimisations sont eux aussi devenus de plus en plus complexes et difficiles à comprendre. Donc développer un outil de caractérisation simple et facile d’utilisation des performances d’applications, serait de grande valeur. Le Modèle Roofline [17] promet un début de réponse à ces critères, mais reste insuffisant pour une caractérisation robuste et détaillée. Dans la première partie de cette thèse, Nous allons développer plusieurs versions améliorées du Roofline, robustes et précises, en passant par une version du Roofline en fonction du temps, des blocs et enfin la nouvelle version du Roofline introduite dans la suite de caractérisation Vtune d’Intel. Pour valider ces modèles, nous utilisons le benchmark LINPACK, STREAM ainsi qu’une mini-application développée au cours de cette thèse, qui résout l’équation de l’advection et qui servira de prototype pour l’évaluation de codes hydrodynamiques explicites. Nous portons aussi cette mini-application sur les co-processeurs d’Intel Xeon Phi KNL et KNC. Dans la deuxième partie de cette thèse nous nous intéressons à la simulation d’impact de vagues, à l’aide de codes industriels compressibles et incompressibles. Nous rajoutons plusieurs fonctionnalités dans le code compressible FluxIC, nous effectuons un chaînage de codes incompressible et compressible et enfin nous introduisons un nouveau schéma numérique appelé liquide incompressible et gaz quasi-compressible, qui permet de réaliser une simulation d’impact d’une vague via un code incompressible avec une correction compressible dans les zones où la compressibilité du gaz est importante.During recent years computer processors have become increasingly complex (multiple levels of cache, vectorization, etc), meaning that the study of performance and optimization is also becoming more complex and difficult to understand. So a simple and easy-to-use model aimed at studying the performance of applications would be of great value. The Roofline model [17] promises to meet this criteria, but it is insufficient for robust and detailed characterization.In the first part of this thesis, several improved versions of the Roofline model, that are more robust and accurate, are developed by going through theRoofline version as a function of time and block, and finally a new Rooflinemodel is implemented in the Intel Vtune characterization suite. To validate thenew models, the LINPACK andtextitSTREAM benchmarks are used, as wellas, a mini-application developed during this thesis that solves the advectionequation and serves as a prototype for the evaluation of explicit hydrodynamicsimulation codes. This mini-application is also ported to the new Intel XeonPhi KNL and KNC co-processors.Simulation of wave impact using compressible and incompressible industrialcodes is the focus of the second part of this thesis. Several functionalities are added to the compressible FluxIC code, and a chaining of compressible andincompressible codes is carried out. Finally, a new numerical scheme called"incompressible liquid and quasi-compressible gas" is introduced, which allowsthe simulation of wave impact using an incompressible code with a compressiblecorrection in areas where gas compressibility is significant

Accélérations algorithmiques pour la simulation numérique d’impacts de vagues. Modèles de type "roofline" pour la caractérisation des performances, application à la CFD

During recent years computer processors have become increasingly complex (multiple levels of cache, vectorization, etc), meaning that the study of performance and optimization is also becoming more complex and difficult to understand. So a simple and easy-to-use model aimed at studying the performance of applications would be of great value. The Roofline model [17] promises to meet this criteria, but it is insufficient for robust and detailed characterization.In the first part of this thesis, several improved versions of the Roofline model, that are more robust and accurate, are developed by going through theRoofline version as a function of time and block, and finally a new Rooflinemodel is implemented in the Intel Vtune characterization suite. To validate thenew models, the LINPACK andtextitSTREAM benchmarks are used, as wellas, a mini-application developed during this thesis that solves the advectionequation and serves as a prototype for the evaluation of explicit hydrodynamicsimulation codes. This mini-application is also ported to the new Intel XeonPhi KNL and KNC co-processors.Simulation of wave impact using compressible and incompressible industrialcodes is the focus of the second part of this thesis. Several functionalities are added to the compressible FluxIC code, and a chaining of compressible andincompressible codes is carried out. Finally, a new numerical scheme called"incompressible liquid and quasi-compressible gas" is introduced, which allowsthe simulation of wave impact using an incompressible code with a compressiblecorrection in areas where gas compressibility is significant.Au cours de ces dernières années les processeurs sont devenus de plus en plus complexes (plusieurs niveaux de cache, vectorisation,...), l’augmentation de la complexité fait que l’étude des performances et les optimisations sont eux aussi devenus de plus en plus complexes et difficiles à comprendre. Donc développer un outil de caractérisation simple et facile d’utilisation des performances d’applications, serait de grande valeur. Le Modèle Roofline [17] promet un début de réponse à ces critères, mais reste insuffisant pour une caractérisation robuste et détaillée. Dans la première partie de cette thèse, Nous allons développer plusieurs versions améliorées du Roofline, robustes et précises, en passant par une version du Roofline en fonction du temps, des blocs et enfin la nouvelle version du Roofline introduite dans la suite de caractérisation Vtune d’Intel. Pour valider ces modèles, nous utilisons le benchmark LINPACK, STREAM ainsi qu’une mini-application développée au cours de cette thèse, qui résout l’équation de l’advection et qui servira de prototype pour l’évaluation de codes hydrodynamiques explicites. Nous portons aussi cette mini-application sur les co-processeurs d’Intel Xeon Phi KNL et KNC. Dans la deuxième partie de cette thèse nous nous intéressons à la simulation d’impact de vagues, à l’aide de codes industriels compressibles et incompressibles. Nous rajoutons plusieurs fonctionnalités dans le code compressible FluxIC, nous effectuons un chaînage de codes incompressible et compressible et enfin nous introduisons un nouveau schéma numérique appelé liquide incompressible et gaz quasi-compressible, qui permet de réaliser une simulation d’impact d’une vague via un code incompressible avec une correction compressible dans les zones où la compressibilité du gaz est importante

High-performance Elliptic Curve Cryptography by Using the CIOS Method for Modular Multiplication

International audienceElliptic Curve Cryptography (ECC) is becoming unavoidable, and should be used for public key protocols. It has gained increasing acceptance in practice due to the significantly smaller bit size of the operands compared to RSA for the same security level. Most protocols based on ECC imply the computation of a scalar multiplication. ECC can be performed in affine, projective, Jacobian or others models of coordinates. The arithmetic in a finite field constitutes the core of ECC Public Key Cryptography. This paper discusses an efficient hardware implementation of scalar multiplication in Jacobian coordinates by using the Coarsely Integrated Operand Scanning method (CIOS) of Montgomery Modular Multiplication (MMM) combined with an effective systolic architecture designed with a two-dimensional array of Processing Elements (PE). As far as we know this is the first implementation of such a design for large prime fields. The proposed architectures are designed for Field Programmable Gate Array (FPGA) platforms. The objective is to reduce the number of clock cycles of the modular multiplication, which implies a good performance for ECC. The presented implementation results focuses on various security levels useful for cryptography. This architecture have been designed in order to use the flexible DSP48 on Xilinx FPGAs. Our architecture for MMM is scalable and depends only on the number and size of words

"hasSignification()": une nouvelle fonction de distance pour soutenir la d\'etection de donn\'ees personnelles

Today with Big Data and data lakes, we are faced of a mass of data that is very difficult to manage it manually. The protection of personal data in this context requires an automatic analysis for data discovery. Storing the names of attributes already analyzed in a knowledge base could optimize this automatic discovery. To have a better knowledge base, we should not store any attributes whose name does not make sense. In this article, to check if the name of an attribute has a meaning, we propose a solution that calculate the distances between this name and the words in a dictionary. Our studies on the distance functions like N-Gram, Jaro-Winkler and Levenshtein show limits to set an acceptance threshold for an attribute in the knowledge base. In order to overcome these limitations, our solution aims to strengthen the score calculation by using an exponential function based on the longest sequence. In addition, a double scan in dictionary is also proposed in order to process the attributes which have a compound name.Comment: in French languag

SecP2I A Secure Multi-party Discovery of Personally Identifiable Information (PII) in Structured and Semi-structured Datasets

International audienc

An efficient and scalable modular inversion/division for public key cryptosystems

International audienc

Characterization of 2D advection solver on Intel architectures and introduction of the“dynamic roofline” model

International audienceDuring recent years computer processors have become increasingly complex (multiple levels of cache, vectorization, etc), meaning that the study of performance and optimization are also becoming more complex and difficult to understand. So a simple and easy-to-use model for studying the performance of applications would be of great value. The roofline model (S.Williams 2009) promises to meet these criteria.In the first part of our presentation we will describe the development of tools showing how to plot the “roofline” for different architectures, and introduce a new methodology, called “dynamic roofline”, for calculation of the number of flops per byte as a function of time, in order to identify parts of a code that contain many calculations and others that have a high load, and data transfer to and from the DRAM.In the second part of this work we will describe the characterization and optimization of a mini-application : a 2d advection equation solver based on a 2nd order scheme in time and space. This standard elementary solver is taken as a prototype (mini application) in order to evaluate the cost of the advection terms in a general hydro-code. The main objective of this work is to evaluate the performance of a fully hybrid implementation using MPI and OpenMP on recent and future Intel CPU (sandy bridge, ivy bridge, haswell, broadwell ) and Xeon Phi processor systems (KNL