Performance of 4096 pixel photon counting chip

A 4096 pixel Photon Counting Chip (PCC) has been developed and tested. It is aimed primarily at medical imaging although it can be used for other applications involving particle counting. The readout chip consists of a matrix of 64 x 64 identical square pixels, whose side measures 170 mm and is bump-bonded to a similar matrix of GaAs or Si pixel diodes covering a sensitive area of 1.18 cm . The electronics in each cell comprises a preamplifier, a discriminator with variable threshold and a 3-bit threshold tune as well as 15-bit counter. Each pixel can be individually addressed for electrical test or masked during acquisition. A shutter allows for switching between the counting and the readout modes and the use of a static logic in the counter enables long data taking periods. Electrical tests of the chip have shown a maximum counting rate of up to 2 MHz in each pixel. The minimum reachable threshold is 1400 e with a variation of 350 e rms that can be reduced to 80 e rms after tuning with the 3-bit adjustment. Electical noise at the input is 170 e rms. Several read-out chips have been bump-bonded to 200 mm thick GaAs detectors. Tests with g-rays and b sources have been carried out. A number of objects have been imaged and 260 mm thick aluminium foil which represents a contrast to the surrounding aire of only 1.9% has been correctly imaged

Progress in development of the readout chip for the ATLAS semiconductor tracker

The development of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS Semiconductor Tracker has entered a pre-production prototyping phase. Following evaluation of the ABCD2T prototype chip, necessary correction in the design have been implemented and the ABCD3T version has been manufactured in the DMILL process. Design issues addressed in the ABCD3T chip and performance of this pre-production prototype are discussed

LHC1: a semiconductor pixel detector readout chip with internal, tunable delay providing a binary pattern of selected events

The Omega3/LHCl pixel detector readout chip comprises a matrix of 128 X 16 readout cells of 50 mu m X 500 mu m and peripheral functions with 4 distinct modes of initialization and operation, together more than 800 000 transistors. Each cell contains a complete chain of amplifier, discriminator with adjustable threshold and fast-OR output, a globally adjustable delay with local fine-tuning, coincidence logic and memory. Every cell can be individually addressed for electrical test and masking, First results have been obtained from electrical tests of a chip without detector as well as from source measurements, The electronic noise without detector is similar to 100 e(-) rms. The lowest threshold setting is close to 2000 e(-) and non-uniformity has been measured to be better than 450 e(-) rms at 5000 e(-) threshold. A timewalk of < 10 ns and a precision of < 6 ns rms on a delay of 2 mu s have been measured. The results may be improved by further optimization

ATLAS pixel detector electronics and sensors

The silicon pixel tracking system for the ATLAS experiment at the Large Hadron Collider is described and the performance requirements are summarized. Detailed descriptions of the pixel detector electronics and the silicon sensors are given. The design, fabrication, assembly and performance of the pixel detector modules are presented. Data obtained from test beams as well as studies using cosmic rays are also discussed

A Readout Chip for a 64 x 64 Pixel Matrix with 15-bit Single Photon Counting

A single Photon Counting pixel detector readout Chip (PCC) has been derived from previous work in the CERN RD19 collaboration for particle physics tracking devices, recently developed for high energy physics experiments. The readout chip is a 64 x 64 matrix of identical 170mm x 170mm cells. It is to be bump-bonded to an equally segmented 1 cm2 matrix of semiconductor sensors, e.g. Si or GaAs. Each readout cell comprises a preamplifier, a discriminator and a 15-bit counter. The input noise is 170 e- rms. At the lowest nominal threshold of 1 400 e- (5.1 keV in Si) the cells exhibit a threshold di stribution with a spread before adjustment of 350 e- rms. Each cell has a 5-bit register which allows masking, test-enable and 3-bit individual threshold adjust. After adjustment the threshold spread is reduced to 80 e- rms. Absolute calibration of the electrically measured equivalent charge can be done once the readout chip is bump-bonded to a detector

A demonstrator analog signal processing circuit in a radiation hard SOI-CMOS technology

It is proposed to develop a demonstrator integrated circuit for particle detector analog signal processing using the advanced 1.2 micron HSOI3-HD Silicon-on-Insulator (SOI) CMOS radiation hard technology of Thomson-TMS, which has recently become accessible for selected civilian applications. The characteristics announced for this process promise survivability after a total dose in excess of 10 Mrad (SiO2) and 10**14 to 10**15 n/cm2, which is probably satisfactory for applications in LHC detector systems. The properties of such a SOI process look promising, in particular regarding speed. In view of the special analog requirements in the particle physics environment,one should verify the analog characteristics before and after irradiation by producing a demonstrator signal processing circuit which incorporates the most vital functional blocks. This demonstrator would consist of a low noise front-end amplifier, a comparator and an analog pipeline element with associated logic, following the scheme of the Hierarchical Analog Readout Pipelined Processor HARP, which has been developed in the framework of the CERN-LAA detector R&D project