The development of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS Semiconductor Tracker has entered a pre-production prototyping phase. Following evaluation of the ABCD2T prototype chip, necessary correction in the design have been implemented and the ABCD3T version has been manufactured in the DMILL process. Design issues addressed in the ABCD3T chip and performance of this pre-production prototype are discussed

Anghinolfi, Francis

Clark, A

Dabrowski, W

Dick, B

Dubbs, T

Eklund, L

French, M

Gannon, W

Grillo, A

Jarron, Pierre

Kaplon, J

Kudlaty, J

La Marra, D

Lacasta, C

Macina, Daniela

Mandic, I

Meddeler, G

Niggli, H

Philips, P W

Spencer, E

Szczygiel, R

Weilhammer, Peter

Zsenei, A

Dabrowski, W.

Anghinolfi, F.

Clark, Allan Geoffrey

Dick, B.

Dubbs, T.

Eklund, L.

French, M.

Gannon, W.

Grillo, A.

Jarron, P.

Kaplon, J.

Kudlaty, J.

Lacasta, C.

La Marra, Daniel

Macina-Buono, Daniela

Mandic, I.

Meddeler, G.

Niggli, H.

Phillips, P. W.

Weilhammer, P.

Spencer, E.

Szczygiel, R.

Zsenei, Andras

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Progress in Development of the Readout Chip for the ATLAS Semiconductor Tracker

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Progress in Development of the Readout Chipfor the ATLAS Semiconductor Tracker.Dąbrowski, W.a (e-mail: W.Dabrowski@ftj.agh.edu.pl), Anghinolfi, F.b, Clark, A.c, Dick, B.c*,Dubbs, T.d, Eklund, L.b, French, M.e, Gannon, W.e, Grillo, A.d, Jarron, P.b, Kaplon, J.b,Kudłaty, J.a #, Lacasta, C.f, LaMarra, D.c, Macina, D.c, Mandic, I.g, Meddeler, G.h, Niggli, H.h,Phillips, P.W.e, Weilhammer, P.b, Spencer, E.d, Szczygieł, R.b, Zsenei, A.ca Faculty of Physics and Nuclear Techniques, UMM, Kraków, Polandb CERN, 1211 Geneva 23, Switzerlandc University of Geneva, Switzerlandd Santa Cruz Institute for Particle Physics, UCSC Santa Cruz, CA, USAe Rutherford Appleton Laboratory, Didcot, UKf IFIC, Valencia, Spaing Jozef Stefan Institute, Ljubljana, Sloveniah Lawrence Berkeley National Laboratory, Berkeley, CA, USA                                                       * visitor from University of Melbourne, Australia.# supported by MPI, Munich, GermanyAbstractThe development of the ABCD chip for the binaryreadout of silicon strip detectors in the ATLASSemiconductor Tracker has entered a pre-productionprototyping phase. Following evaluation of the ABCD2Tprototype chip, necessary correction in the design havebeen implemented and the ABCD3T version has beenmanufactured in the DMILL process. Design issuesaddressed in the ABCD3T chip and performance of thispre-production prototype are discussed.I. INTRODUCTIONThe ABCD design is one of the two options of thebinary readout architecture which have been developedfor the ATLAS SCT [1-3]. Recently, based on theperformance of the ABCD2T prototype, this option hasbeen chosen as a baseline. The ABCD chip developed andmanufactured in the DMILL process comprises in a singlechip all blocks of the binary readout architecture; thefront-end circuit, discriminator, binary pipeline,derandomizing buffer, data compression logic, and thereadout control logic, as required for the ATLAS SCT.For the binary architecture one of the most criticalissues is the uniformity of parameters of the front-endcircuit and matching of the discriminator threshold. Amajor improvement of the ABCD2T performance hasbeen achieved by implementation of individual thresholdcorrection in every channel using a 4-bit digital-to-analogue converter (TrimDAC) per channel.The ABCD2T version has met all basic requirementsof the ATLAS SCT, however, detailed evaluation of theABCD2T chips, including extensive radiation testing,pointed to some possible improvements. Theseimprovements, which concern mainly improvement of theradiation resistance and reduction of the design sensitivityto variation of the process parameters, have beenimplemented in the ABCD3T version. The later aspect isimportant for large volume production as it may impactthe production yield. An overview of the ABCD architecture and of theperformance of  the ABCD2T prototype can be found inearlier publications [1,4]. In this paper we focus mainlyon the specific issues which have been addressed in theABCD3T design.In the front-end circuit of the ABCD2T we haveidentified two points which compromised slightlyperformance of that prototype, namely: (i) the internalcalibration circuitry showed non-linearity for low inputcharges, (ii) TrimDACs response curves appeared to benon-linear and exhibited large spread from channel-to-channel. The non-linearity of the calibration circuitry,although not critical, makes the calibration proceduremore complicated than necessary.  The source of  thenon-linearity has been identified as parasitic chargeinjection from CMOS switches employed in thecalibration circuit.A non-linear response of the TrimDAC is not aserious problem as the trimming procedure is based onmeasurement of the TrimDAC characteristics and usingthese results in a look-up table. A consequence of thenon-linearity is a slightly worst matching of the thresholdcompared to what one can expect assuming perfectlylinear response curves of this circuit. More important,however, is that TrimDACs in some channels become sonon-linear that those channels fall outside the trimmingrange. Since for good chips we require all the channels tobe within the specification that effect, if not corrected,would impact significantly the yield in the production.The source of the problem has been identified in thedesign and an easy correction has been found.II. FRONT-END PERFORMANCEBasic performance of the front-end circuit in theABCD design, in particular the noise, has been discussedin previous papers. In this paper we focus on the twoissues, which have been improved in the ABCD3T designcompared to the ABCD2T, i.e. linearity of the calibrationcircuit and TrimDAC characteristics.A. Internal calibration circuitInternal calibration circuit is foreseen to be used atvarious steps of chip testing and module testing as well asfor threshold calibration in the experiment. A firstpurpose of this circuit is providing testability of the chip.It allows to take measurements of analogue parameters;gain, noise, offset, time walk and TrimDACcharacteristics for every channel during of waferscreening without supplying a precise analogue signal tothe chips. All these measurements are then repeated forcomplete modules equipped with 12 ABCD chips each.For the binary architecture as implemented in theABCD design the linearity of the front-end circuit is not acritical issue. However, a good absolute precision isrequired for setting the working threshold in thediscriminators which impact the efficiency and noiseoccupancy. The threshold setting will be based oncalibration using internal calibration circuit and so theprecision of this circuit around the nominal thresholdsetting, i.e. 1 fC, is a key issue. As mentioned before thecalibration circuit in the ABCD2T design exhibited non-linear behaviour for low input charges which has beenidentified as parasitic charge injection in the choppercircuit.The response curves for 128 channels in one chipmeasured using internal calibration circuit are shown inFig.1. The measurements were taken starting with aninput charge of  0.5 fC of the input charge. The points  at0 fC obtained from the noise occupancy scan are includedin the plot. The response curves are satisfactorily linearwithin a range between 0.5 fC and 4 fC which allows touse simple linear fits when performing calibration of thethreshold in the range around 1 fC.Input Charge (fC)0 1 2 3 4 5 6 7 850% (mV)050100150200250300350400450500Response Curve - No trimmedFigure 1: Response curves for 128 channels in one ABCD3Tchip before threshold correction.B. TrimDACThe TrimDAC circuit as implemented in theABCD2T chip has been proved to be an efficient solutionto correct the threshold spread. The functionality of thiscircuit has been demonstrated [1], however, itsperformance could still be improved. First, thecharacteristics of the TrimDACs exhibited large non-linearity. The source of the non-linearity has beenidentified and a simple correction, without changing theconcept of the circuit, has been implemented in theABCD3T design. Second, radiation tests showed that thespread of the discriminator offset increased significantlyafter irradiation and exceeded the range of theTrimDACs. In order to not compromise the precision ofthreshold correction for non-irradiated chips and toguarantee that for fully irradiated chips all the channelscan be corrected, a set of ranges has been implemented inthe ABCD3T design.Fig. 2 shows the characteristics of the TrimDACs for128 channels in one ABCD3T chip for the minimumrange set. One can see that the characteristics aresatisfactorily  linear given the 4-bit resolution of theTrimDAC. The minimum range of the TrimDAC issufficient  to  cover   the  discriminator  offset  spread.Fig. 3. shows the characteristics of the TrimDAC in asingle channel for 4 different range sets.Trim DAC Correction0 2 4 6 8 10 12 1450% points (mV)100120140160180200220240Range 0Figure 2: Typical characteristics of the TrimDACs for 128channels in the ABCD3T chipTrim DAC Correction0 2 4 6 8 10 12 1450% points (mV)050100150200250300350400450500Trim Dac characteristics - Channel 32Figure 3: Characteristics of the TrimDAC in a single channelfor four different range sets.In order to confirm the functionality and performanceof the TrimDACs we performed the trimming procedureas it is foreseen in the experiment. The distribution of theChannel number0 20 40 60 80 100 12050 % point (mV)0102030405060708090Matching  1 fC - No trimmed50% point (mV)30 40 50 60 70 80 90 100 110 120 130024681012141650 % point spread  1 fC - No trimmed Nent = 128    Mean  =  69.99RMS   =  7.409Chi2 / ndf = 8.987 / 16Constant = 12.75 +- 1.502 Mean     = 70.06 +- 0.6594 Sigma    = 7.474 +- 0.5989 Figure 4: Distribution of threshold for 128 channels in oneABCD3T chip before threshold correction.Channel number0 20 40 60 80 100 12050 % point (mV)020406080100Matching  1fC - Trimmed  1 fC50% point (mV)80 85 90 95 100 105 110 115 120 125 1300510152025303550 % point spread  1 fC - Trimmed  1 fC Nent = 128    Mean  =  105.7RMS   =  1.455Chi2 / ndf = 2.136 / 5Constant = 33.97 +- 3.398 Mean     = 105.7 +- 0.1359 Sigma    = 1.476 +- 0.06967 Figure 5: Distribution of threshold for 128 channels in oneABCD3T chip after threshold correction.threshold in 128 channels in one chip for 1 fC inputcharge is shown in Fig. 4. The rms value is 7.4 mV. Thesame distribution after threshold correction is shown inFig. 5. The spread has been reduced now down to 1.5 mVrms which is the value one can expect given theTrimDAC step of 4 mV. The spread of the threshold isequivalent to ENC of 180 e- rms, which is completelynegligible compared to the typical noise of 1400 e- rmsfor a module with long silicon strips, as foreseen for theATLAS SCT.III. RADIATION EFFECTSThe radiation effects in the DMILL technology and inthe ABCD design have been discussed in the previouspaper [4]. The DMILL technology is qualified as aradiation resistant one, however, the radiation levelsexpected for the SCT detector in the ATLAS experimentsexceed the upper limits of those specified for the DMILLprocess, i.e.  10 Mrad  of  the  ionising  dose  and1×1014 n/cm2 1 MeV eq. neutron fluence. In addition, ifone takes into account very advanced requirementsregarding the noise, speed and power consumption of theABCD chip, it becomes obvious that radiation effects inthe basic devices, although limited, can not be ignored.A. Total dose effectsThe radiation hardness of the ABCD design has beenevaluated in numerous tests in various radiationenvironments. The performance of the front-end circuit isaffected by the major radiation effect in bipolartransistors, i.e. degradation of the current gain factor β.As a results the parallel noise in the front-end increases.This effect has been taken into account from thebeginning of the ABCD project.Fig. 6a. shows evolution of the parallel noise vs.particle fluence during irradiation of a hybrid with 6ABCD3T chips in 24 GeV proton beam. Each curverepresents the average for 128 channels in one chip. Theresults of neutron irradiation performed in a reactor areshown in Fig. 6b. In both cases we observe an increase ofthe parallel noise which is due to the increase of the shotnoise of the base current when the input stage is operatedwith a constant collector current. As discussed in previouspaper [1], the increase of the parallel noise has a smalleffect on the total noise when the chips are connected tolong strips and the noise is dominated by the series noise.Another effect, which was not expected from thebeginning but has been observed systematically in allradiation tests, is an increase of the offset spread in thediscriminator. The source of this effect has beenidentified as worsening of resistor matching. Theevolution of the offset spread vs. proton fluence (a), andneutron fluence (b), for 6 irradiated ABCD3T chips isshown in Fig. 7.  The offset spread increases by a factor3-4 after proton irradiation and by a factor about 2 afterneutron irradiation. The same effect was observed beforefor the ABCD2T chips.Figure 6: Increase of the parallel noise vs. particle fluence:(a) protons,  (b) neutrons.Figure 7: Increase of the discriminator offset spread vs. particlefluence: (a) protons, (b) neutrons.A major total dose effect expected in the digital partof the ABCD design is slowing down. The post-radiationdrifts of the parameters of MOS devices as well as thevariation of the process parameters have been anticipatedand a sufficient speed margin has been foreseen in thedesign. Typical degradation of the maximum clockfrequency vs. total ionising dose for ABCD3T chip isshown in Fig. 8. Since the test was done with a high doserate the standard high temperature annealing wasperformed in order to simulate irradiation with a low doserate. After full dose of 10 Mrad the maximum clockfrequency is 52 MHz at nominal supply voltage of 4 V,compared to the required 40 MHz. Compared to theABCD2T design the speed margin has been improved byabout 10 MHz by tuning the timing in various blocks ofthe circuit. In the ABCD2T chips excessive leakage current wasobserved after irradiation. The source of the leakage hasbeen traced down to a particular latch structure which wasused in various block of the chip. The design has beencorrected in the ABCD3T version. The evolution of thedigital supply current after irradiation up to the nominaldose of 10 Mrad and annealing is shown in Fig. 9. Arapid increase of the supply current is observedimmediately after irradiation with high dose rate. Theexcessive current anneals then very quickly down to theultimate level, which is even below the initial value.Max_Freq [MHz]01020304050607080901000Mrads 10Mrads + 9H25deg10Mrads + 48H25deg10Mrads + 48H25deg + 1 weekhigh tempFigure 8: Evolution of the maximum cock frequency afterirradiation and annealing.IDD [mA]01020304050607080901000Mrads 10Mrads 10Mrads + 9H25deg10Mrads + 48H25deg10Mrads + 48H25deg + 1week high tempFigure 9: Evolution of the digital current supply  afterirradiation and annealing.(a)(b)(a)(b)B. Single event effectsSince the ABCD chips will be exposed in theexperiment mainly to high energy charged particles andneutrons single event effects (SEE) are equally importantas the total dose effects. Given the architecture of theABCD chip there are two major types of digital blockswhich may be affected by SEE, namely the pipeline andthe static registers which contain information about chipconfiguration and settings of operating points. Any bitflip in the pipeline causes a single data error and thus tobe compared with the noise rate expected from the front-end circuit. Such errors will not require any intervention.The errors in static registers may lead to changes of staticbiases in the front-end, setting of the threshold or changesof operation mode. In order to recover from such errors itwill be needed to reload the chip configuration.The sensitivity of the ABCD chip to the SEE has beentested in 24 GeV proton beam and in 200 MeV pionbeam. The results from both tests are fully consistent asone can expect assuming that for the DMILL process theenergy transfer threshold for SEE is well below 200 MeV.An example of data is shown in Fig. 10. The plot showsthe number of SEE counted in the pipeline of one chipwhile  the   beam   was  scanned  across  the  hybrid  withtime (proportional to spill number)Figure 10: Measurement of SEE in the pipeline duringirradiation proton beam.6 ABCD2T chips. The upper plot shows the SEE countsperformed within the beam spills and the lower plotshows the SEE counts outside the beam spills.From such measurements we have estimated the crosssections for two types of memory cells used in the ABCDdesign. For the pipeline in which dynamic memory cellsare used the SEE rate has been measured as 5×10-7/bit/s.For the static registers the SEE rate has been estimated as1×10-7/bit/s. None of these numbers seems to create aproblem for operation of the SCT in the particle fluxes aspresently estimated.IV. SUMMARYThe ABCD3T chip is the final version of the binaryreadout for the ATLAS Semiconductor Tracker. Itincorporates fixes of minor imperfections identified in theprevious prototypes. The ABCD2T and ABCD3T chipshave been used extensively for building complete SCTmodules used then in the beam tests and the multi-modulesystem test. About 100 ABCD2T and ABCD3T chipshave been irradiated in various tests up to the total dosesas expected in the ATLAS SCT. All these tests showedconsistent results. An efficient wafer screening systemhas been developed and used for testing wafers fromprototype batches.V. REFERENCES1. W. Dabrowski et al., Design and Performance of theABCD Chip for the Binary Readout of Silicon StripDetectors in the ATLAS Semiconductor Tracker.Proc. of the IEEE Nucl. Science Symposium, Seattle,IEEE Trans. on Nucl. Sci., in print.2. T. Dubbs et al., The Development of the CAFE-P/CAFE-M Bipolar Chips for the AtlasSemiconductor Tracker. Proc. of the Fifth Workshopon Electronics for LHC Experiments, Snowmass,Colorado, USA September 20-24, 1999,CERN/LHCC/99-03, 29 Oct 1999, p. 123.3. D. Campbell et al., The Development of the Rad-Hard CMOS Chip for the Binary Readout of theATLAS Semiconductor Tracker. Proc. of the FifthWorkshop on Electronics for LHC Experiments,Snowmass, Colorado, USA September 20-24, 1999,CERN/LHCC/99-03, 29 Oct 1999, p. 152.4. W. Dabrowski et al. Radiation Hardness of theABCD Chip for the Binary Readout of Silicon StripDetectors in the ATAS Semiconductor Tracker. Proc.of the Fifth Workshop on Electronics for LHCExperiments, Snowmass, Colorado, USA September20-24,  1999,  CERN/LHCC/99-03,  29 Oct  1999,p. 113.

Progress in development of the readout chip for the ATLAS semiconductor tracker

Progress in development of the readout chip for the ATLAS semiconductor tracker

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