Recent Advances in High-k Nanocomposite Materials for Embedded Capacitor Applications

©2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or distribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.DOI: 10.1109/TDEI.2008.4656240In this paper, a wide variety of high dielectric constant (k) composite materials which have been developed and evaluated for embedded capacitor application are reviewed. Current research efforts toward achieving high dielectric performance including highk and low dielectric loss for polymer composites are presented. New insights into the effect of unique properties of the nanoparticle filler, filler modification and the dispersion between filler and polymer matrix on the dielectric properties of the nanocomposites are discussed in details

Double-Layer No-Flow Underfill Process for Flip-Chip Applications

©2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or distribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.No-flow underfill technology shows potential advances over the conventional underfill technology toward a low-cost flop-chip underfill process. However, due to the filler entrapment in between solder bumps and contact pads on board, no-flow underfills are mostly unfilled or filled with very low filler loading. The high coefficient of thermal expansion (CTE) of the polymer material has significantly lowered the reliability of flip chip assembly and has limited its application to large chip assemblies. This paper presents a double-layer no-flow underfill process approach to incorporate silica filler into a no-flow underfill. Two layers of underfills are applied on to the substrate before chip placement. The bottom underfill layer facing the substrate is fluxed and unfilled; the upper layer facing the chip is filled with silica fillers. The total filler loading of the mixture is estimated to be around 55 wt%. The material properties of each layer of underfills, the underfill mixture, and a control unfilled underfill are characterized using differential scanning calorimeter (DCS), thermo-mechanical analyzer (TMA), dynamic mechanical analyzer (DMA), and a stress rheometer. FB250 daisy-chained test chips are assembled on FR-4 boards using the novel approach. A 100% assembly yield of solder Interconnect is achieved with the double-layer no-flow underfill while in the single-layer no-flow underfill process, no solder joint yield is observed. Scanning electronic microscope (SEM) and optical microscope are used to investigate the cross-section of both assemblies. A US provisional patent has been filed for this invention

An equitriangular integral transform and its applications

Equitriangular integral transform for solving boundary value problems in viscous flow and heat transfe

Fault-tolerant linear optics quantum computation by error-detecting quantum state transfer

A scheme for linear optical implementation of fault-tolerant quantum computation is proposed, which is based on an error-detecting code. Each computational step is mediated by transfer of quantum information into an ancilla system embedding error-detection capability. Photons are assumed to be subjected to both photon loss and depolarization, and the threshold region of their strengths for scalable quantum computation is obtained, together with the amount of physical resources consumed. Compared to currently known results, the present scheme reduces the resource requirement, while yielding a comparable threshold region.Comment: 9 pages, 7 figure

Euler equation of the optimal trajectory for the fastest magnetization reversal of nano-magnetic structures

Based on the modified Landau-Lifshitz-Gilbert equation for an arbitrary Stoner particle under an external magnetic field and a spin-polarized electric current, differential equations for the optimal reversal trajectory, along which the magnetization reversal is the fastest one among all possible reversal routes, are obtained. We show that this is a Euler-Lagrange problem with constrains. The Euler equation of the optimal trajectory is useful in designing a magnetic field pulse and/or a polarized electric current pulse in magnetization reversal for two reasons. 1) It is straightforward to obtain the solution of the Euler equation, at least numerically, for a given magnetic nano-structure characterized by its magnetic anisotropy energy. 2) After obtaining the optimal reversal trajectory for a given magnetic nano-structure, finding a proper field/current pulse is an algebraic problem instead of the original nonlinear differential equation

Film-stability in a vertical rotating tube with a core-gas flow

Linear hydrodynamic stability of interface between Newtonian liquid film and core fluid under influence of swirl, core flow, and gravit